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Author SHA1 Message Date
a0711a5e13 successful test of module omdazz_WS2812b.v 2026-08-07 20:49:16 +03:00
cd96a065b8 added led_mask 2026-08-07 20:24:04 +03:00
6c8f8e7531 top.v has been added 2026-08-07 19:40:04 +03:00
4dadc21523 Merge pull request 'Merge pull request 'master1' (#2) from master1 into master' (#3) from master into master1
Reviewed-on: #3
2026-08-07 19:11:07 +03:00
e509bcd442 top.v has been added 2026-08-07 19:20:33 +03:00
e68f569ee2 Merge remote-tracking branch 'origin/master' into master1
# Conflicts:
#	omdazz_WS2812b.qsf
#	omdazz_WS2812b.v
#	top.v
2026-08-07 19:18:19 +03:00
3aa5e6bfac top.v has been added 2026-08-07 19:15:17 +03:00
4f9019b544 Merge pull request 'master1' (#2) from master1 into master
Reviewed-on: #2
2026-08-07 19:09:34 +03:00
83f00f9ff3 driver WS2812b moved to the other module 2026-08-07 17:46:11 +03:00
3 changed files with 39 additions and 9 deletions

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@ -2,8 +2,10 @@ module omdazz_WS2812b #(
parameter integer WS2812_NUM = 10 - 1, parameter integer WS2812_NUM = 10 - 1,
parameter integer WS2812_WIDTH = 24, parameter integer WS2812_WIDTH = 24,
parameter integer CLK_FRE = 50_000_000 parameter integer CLK_FRE = 50_000_000
//parameter [WS2812_NUM:0] LED_MASK
)( )(
input wire CLOCK_50, input wire CLOCK_50,
input wire [WS2812_NUM-1:0] LED_MASK,
output reg WS2812 output reg WS2812
); );
@ -27,6 +29,10 @@ reg [ 8:0] data_send = 0; // amount of data words sent // increase it for larg
reg [31:0] clk_count = 0; // delay control reg [31:0] clk_count = 0; // delay control
reg [23:0] WS2812_data = 24'd1; // WS2812 color data reg [23:0] WS2812_data = 24'd1; // WS2812 color data
wire send_bit;
assign send_bit = WS2812_data[bit_send] & LED_MASK[data_send];
//assign send_bit = (data_send == 0) ? WS2812_data[bit_send] : 1'b0;
always@(posedge CLOCK_50) always@(posedge CLOCK_50)
case (state) case (state)
RESET:begin RESET:begin
@ -59,7 +65,7 @@ always@(posedge CLOCK_50)
BIT_SEND_HIGH:begin BIT_SEND_HIGH:begin
WS2812 <= 1; WS2812 <= 1;
if (WS2812_data[bit_send]) if (send_bit)
if (clk_count < DELAY_1_HIGH) if (clk_count < DELAY_1_HIGH)
clk_count <= clk_count + 1; clk_count <= clk_count + 1;
else begin else begin
@ -78,7 +84,7 @@ always@(posedge CLOCK_50)
BIT_SEND_LOW:begin BIT_SEND_LOW:begin
WS2812 <= 0; WS2812 <= 0;
if (WS2812_data[bit_send]) if (send_bit)
if (clk_count < DELAY_1_LOW) if (clk_count < DELAY_1_LOW)
clk_count <= clk_count + 1; clk_count <= clk_count + 1;
else begin else begin

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@ -6,6 +6,6 @@ Page_0 0x00000000 0x00059D8A
Notes: Notes:
- Data checksum for this conversion is 0x1A5EBC7A - Data checksum for this conversion is 0x1A5DDC5D
- All the addresses in this file are byte addresses - All the addresses in this file are byte addresses

30
top.v
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@ -1,14 +1,38 @@
module top( module top(
input wire CLOCK_50, input wire CLOCK_50,
input wire [4:4] D_INP,
output wire WS2812_OUT output wire WS2812_OUT
); );
localparam integer LED_NUM = 10;
localparam integer TICK_1SEC = 50_000_000;
localparam integer COUNTER_WIDTH = 26;
reg [COUNTER_WIDTH-1:0] sec_count;
reg [LED_NUM-1:0] led_mask;
initial begin
sec_count = 0;
led_mask = 10'b0000000001;
end
always @(posedge CLOCK_50) begin
if (sec_count == TICK_1SEC - 1) begin
sec_count <= 0;
// LED0 -> LED1 -> ... -> LED9 -> LED0
led_mask <= {led_mask[LED_NUM-2:0], led_mask[LED_NUM-1]};
end
else begin
sec_count <= sec_count + 1'b1;
end
end
omdazz_WS2812b #( omdazz_WS2812b #(
.WS2812_NUM(10 - 1), .WS2812_NUM(LED_NUM),
.CLK_FRE(50_000_000) .CLK_FRE (50_000_000)
) u_ws2812 ( ) u_ws2812 (
.CLOCK_50(CLOCK_50), .CLOCK_50(CLOCK_50),
.LED_MASK(led_mask),
.WS2812 (WS2812_OUT) .WS2812 (WS2812_OUT)
); );