39 lines
907 B
Verilog
39 lines
907 B
Verilog
module top(
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input wire CLOCK_50,
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output wire WS2812_OUT
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);
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localparam integer LED_NUM = 10;
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localparam integer TICK_1SEC = 50_000_000;
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localparam integer COUNTER_WIDTH = 26;
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reg [COUNTER_WIDTH-1:0] sec_count;
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reg [LED_NUM-1:0] led_mask;
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initial begin
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sec_count = 0;
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led_mask = 10'b0000000001;
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end
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always @(posedge CLOCK_50) begin
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if (sec_count == TICK_1SEC - 1) begin
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sec_count <= 0;
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// LED0 -> LED1 -> ... -> LED9 -> LED0
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led_mask <= {led_mask[LED_NUM-2:0], led_mask[LED_NUM-1]};
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end
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else begin
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sec_count <= sec_count + 1'b1;
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end
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end
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omdazz_WS2812b #(
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.WS2812_NUM(LED_NUM),
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.CLK_FRE (50_000_000)
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) u_ws2812 (
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.CLOCK_50(CLOCK_50),
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.LED_MASK(led_mask),
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.WS2812 (WS2812_OUT)
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);
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endmodule |