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driver WS2812b moved to the other module

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pavel 2026-08-07 17:46:11 +03:00
parent 4d0d51eefc
commit 83f00f9ff3
3 changed files with 119 additions and 90 deletions
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7
omdazz_WS2812b.qsf
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@ -61,5 +61,8 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WS2812
set_location_assignment PIN_23 -to CLOCK_50 set_location_assignment PIN_23 -to CLOCK_50
set_location_assignment PIN_31 -to D_INP[4] set_location_assignment PIN_31 -to D_INP[4]
set_location_assignment PIN_42 -to WS2812 set_location_assignment PIN_42 -to WS2812
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name CDF_FILE output_files/Chain1.cdf set_global_assignment -name CDF_FILE output_files/Chain3.cdf
set_global_assignment -name CDF_FILE output_files/Chain5.cdf
set_global_assignment -name VERILOG_FILE top.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

187
omdazz_WS2812b.v
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@ -1,100 +1,111 @@
module omdazz_WS2812b( module omdazz_WS2812b #(
input CLOCK_50, parameter integer WS2812_NUM = 10 - 1,
input [4:4] D_INP, // 3 (ADCHub1), 4 (ADCHub2) - используются parameter integer WS2812_WIDTH = 24,
output reg WS2812 // output interface to WS2812 parameter integer CLK_FRE = 50_000_000
)(
input wire CLOCK_50,
output reg WS2812
); );
parameter WS2812_NUM = 10 - 1 ; // number of WS2812 LEDs (1, counting from 0) localparam integer DELAY_1_HIGH = 40 - 1; // 0.8 us @ 50 MHz
parameter WS2812_WIDTH = 24 ; // WS2812 data bit width localparam integer DELAY_1_LOW = 22 - 1; // 0.45 us @ 50 MHz
parameter CLK_FRE = 50_000_000; localparam integer DELAY_0_HIGH = 20 - 1; // 0.4 us @ 50 MHz
parameter F_SCALE = 50 / 27; // conversion factor from 27 MHz to 50 MHz localparam integer DELAY_0_LOW = 43 - 1; // 0.85 us @ 50 MHz
localparam integer DELAY_RESET = 3000 - 1; // 60 us @ 50 MHz
parameter DELAY_1_HIGH = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1; localparam RESET = 2'd0;
parameter DELAY_1_LOW = (CLK_FRE / 1_000_000 * 40 / 100 * F_SCALE) - 1; localparam DATA_SEND = 2'd1;
parameter DELAY_0_HIGH = (CLK_FRE / 1_000_000 * 40 / 100 * F_SCALE) - 1; localparam BIT_SEND_HIGH = 2'd2;
parameter DELAY_0_LOW = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1; localparam BIT_SEND_LOW = 2'd3;
parameter DELAY_RESET = (CLK_FRE / 10 * F_SCALE) - 1;
parameter RESET = 0; // state machine declaration reg [1:0] state = RESET;
parameter DATA_SEND = 1; reg [8:0] bit_send = 0;
parameter BIT_SEND_HIGH = 2; reg [8:0] data_send = 0;
parameter BIT_SEND_LOW = 3; reg [31:0] clk_count = 0;
reg [ 1:0] state = 0; // synthesis preserve // main state machine control // Формат WS2812: обычно GRB, отправка старшим битом вперёд
reg [ 8:0] bit_send = 0; // amount of bits sent // increase it for larger LED strips/matrix reg [23:0] WS2812_data = 24'h000001;
reg [ 8:0] data_send = 0; // amount of data words sent // increase it for larger LED strips/matrix
reg [31:0] clk_count = 0; // delay control
reg [23:0] WS2812_data = 24'd1; // WS2812 color data
always@(posedge CLOCK_50) always @(posedge CLOCK_50) begin
case (state) case (state)
RESET:begin
WS2812 <= 0;
if (clk_count < DELAY_RESET) RESET: begin
clk_count <= clk_count + 1; WS2812 <= 1'b0;
else begin
clk_count <= 0;
WS2812_data <= {WS2812_data[22:0],WS2812_data[23]};// color shifting for cyclic
state <= DATA_SEND;
end
end
DATA_SEND: if (clk_count < DELAY_RESET)
if (data_send == WS2812_NUM && bit_send == WS2812_WIDTH)begin clk_count <= clk_count + 1'b1;
data_send <= 0; else begin
bit_send <= 0; clk_count <= 0;
state <= RESET; // Смена цвета после передачи очередного кадра
end WS2812_data <= {WS2812_data[22:0], WS2812_data[23]};
else if (bit_send < WS2812_WIDTH) begin state <= DATA_SEND;
state <= BIT_SEND_HIGH; end
end end
else begin// if (bit_send == WS2812_WIDTH)
data_send <= data_send + 1;
bit_send <= 0;
state <= BIT_SEND_HIGH;
end
BIT_SEND_HIGH:begin
WS2812 <= 1;
if (WS2812_data[bit_send]) DATA_SEND: begin
if (clk_count < DELAY_1_HIGH) if ((data_send == WS2812_NUM) &&
clk_count <= clk_count + 1; (bit_send == WS2812_WIDTH)) begin
else begin data_send <= 0;
clk_count <= 0; bit_send <= 0;
state <= BIT_SEND_LOW; state <= RESET;
end end
else else if (bit_send < WS2812_WIDTH) begin
if (clk_count < DELAY_0_HIGH) state <= BIT_SEND_HIGH;
clk_count <= clk_count + 1; end
else begin else begin
clk_count <= 0; data_send <= data_send + 1'b1;
state <= BIT_SEND_LOW; bit_send <= 0;
end state <= BIT_SEND_HIGH;
end end
end
BIT_SEND_LOW:begin BIT_SEND_HIGH: begin
WS2812 <= 0; WS2812 <= 1'b1;
if (WS2812_data[bit_send]) if (WS2812_data[WS2812_WIDTH - 1 - bit_send]) begin
if (clk_count < DELAY_1_LOW) if (clk_count < DELAY_1_HIGH)
clk_count <= clk_count + 1; clk_count <= clk_count + 1'b1;
else begin else begin
clk_count <= 0; clk_count <= 0;
state <= BIT_SEND_LOW;
end
end
else begin
if (clk_count < DELAY_0_HIGH)
clk_count <= clk_count + 1'b1;
else begin
clk_count <= 0;
state <= BIT_SEND_LOW;
end
end
end
bit_send <= bit_send + 1; BIT_SEND_LOW: begin
state <= DATA_SEND; WS2812 <= 1'b0;
end
else if (WS2812_data[WS2812_WIDTH - 1 - bit_send]) begin
if (clk_count < DELAY_0_LOW) if (clk_count < DELAY_1_LOW)
clk_count <= clk_count + 1; clk_count <= clk_count + 1'b1;
else begin else begin
clk_count <= 0; clk_count <= 0;
bit_send <= bit_send + 1'b1;
bit_send <= bit_send + 1; state <= DATA_SEND;
state <= DATA_SEND; end
end end
end else begin
endcase if (clk_count < DELAY_0_LOW)
endmodule clk_count <= clk_count + 1'b1;
else begin
clk_count <= 0;
bit_send <= bit_send + 1'b1;
state <= DATA_SEND;
end
end
end
default: state <= RESET;
endcase
end
endmodule

15
top.v Normal file
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@ -0,0 +1,15 @@
module top(
input wire CLOCK_50,
input wire [4:4] D_INP,
output wire WS2812_OUT
);
omdazz_WS2812b #(
.WS2812_NUM(10 - 1),
.CLK_FRE(50_000_000)
) u_ws2812 (
.CLOCK_50(CLOCK_50),
.WS2812 (WS2812_OUT)
);
endmodule