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omdazz_WS2812b.qpf
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omdazz_WS2812b.qpf
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 17:00:54 August 07, 2026
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "13.0"
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DATE = "17:00:54 August 07, 2026"
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# Revisions
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PROJECT_REVISION = "omdazz_WS2812b"
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65
omdazz_WS2812b.qsf
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omdazz_WS2812b.qsf
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 17:00:54 August 07, 2026
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# omdazz_WS2812b_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE6E22C8
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set_global_assignment -name TOP_LEVEL_ENTITY omdazz_WS2812b
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:00:54 AUGUST 07, 2026"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name SEARCH_PATH output_files/
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name VERILOG_FILE omdazz_WS2812b.v
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D_INP[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WS2812
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set_location_assignment PIN_23 -to CLOCK_50
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set_location_assignment PIN_31 -to D_INP[4]
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set_location_assignment PIN_42 -to WS2812
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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omdazz_WS2812b.v
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omdazz_WS2812b.v
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module omdazz_WS2812b(
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input CLOCK_50,
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input [4:4] D_INP, // 3 (ADCHub1), 4 (ADCHub2) - используются
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output reg WS2812 // output interface to WS2812
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);
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parameter WS2812_NUM = 10 - 1 ; // number of WS2812 LEDs (1, counting from 0)
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parameter WS2812_WIDTH = 24 ; // WS2812 data bit width
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parameter CLK_FRE = 50_000_000;
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parameter F_SCALE = 50 / 27; // conversion factor from 27 MHz to 50 MHz
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parameter DELAY_1_HIGH = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1;
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parameter DELAY_1_LOW = (CLK_FRE / 1_000_000 * 40 / 100 * F_SCALE) - 1;
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parameter DELAY_0_HIGH = (CLK_FRE / 1_000_000 * 40 / 100 * F_SCALE) - 1;
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parameter DELAY_0_LOW = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1;
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parameter DELAY_RESET = (CLK_FRE / 10 * F_SCALE) - 1;
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parameter RESET = 0; // state machine declaration
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parameter DATA_SEND = 1;
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parameter BIT_SEND_HIGH = 2;
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parameter BIT_SEND_LOW = 3;
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reg [ 1:0] state = 0; // synthesis preserve // main state machine control
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reg [ 8:0] bit_send = 0; // amount of bits sent // increase it for larger LED strips/matrix
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reg [ 8:0] data_send = 0; // amount of data words sent // increase it for larger LED strips/matrix
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reg [31:0] clk_count = 0; // delay control
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reg [23:0] WS2812_data = 24'd1; // WS2812 color data
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always@(posedge CLOCK_50)
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case (state)
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RESET:begin
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WS2812 <= 0;
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if (clk_count < DELAY_RESET)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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WS2812_data <= {WS2812_data[22:0],WS2812_data[23]};// color shifting for cyclic
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state <= DATA_SEND;
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end
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end
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DATA_SEND:
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if (data_send == WS2812_NUM && bit_send == WS2812_WIDTH)begin
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data_send <= 0;
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bit_send <= 0;
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state <= RESET;
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end
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else if (bit_send < WS2812_WIDTH) begin
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state <= BIT_SEND_HIGH;
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end
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else begin// if (bit_send == WS2812_WIDTH)
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data_send <= data_send + 1;
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bit_send <= 0;
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state <= BIT_SEND_HIGH;
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end
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BIT_SEND_HIGH:begin
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WS2812 <= 1;
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if (WS2812_data[bit_send])
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if (clk_count < DELAY_1_HIGH)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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state <= BIT_SEND_LOW;
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end
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else
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if (clk_count < DELAY_0_HIGH)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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state <= BIT_SEND_LOW;
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end
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end
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BIT_SEND_LOW:begin
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WS2812 <= 0;
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if (WS2812_data[bit_send])
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if (clk_count < DELAY_1_LOW)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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bit_send <= bit_send + 1;
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state <= DATA_SEND;
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end
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else
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if (clk_count < DELAY_0_LOW)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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bit_send <= bit_send + 1;
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state <= DATA_SEND;
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end
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end
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endcase
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endmodule
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11
output_file.map
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output_file.map
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BLOCK START ADDRESS END ADDRESS
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Page_0 0x00000000 0x00059D8A
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Notes:
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- Data checksum for this conversion is 0x1A5EBC7A
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- All the addresses in this file are byte addresses
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