111 lines
3.6 KiB
Verilog
111 lines
3.6 KiB
Verilog
module omdazz_WS2812b #(
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parameter integer WS2812_NUM = 10 - 1,
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parameter integer WS2812_WIDTH = 24,
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parameter integer CLK_FRE = 50_000_000
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)(
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input wire CLOCK_50,
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output reg WS2812
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);
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localparam integer DELAY_1_HIGH = 40 - 1; // 0.8 us @ 50 MHz
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localparam integer DELAY_1_LOW = 22 - 1; // 0.45 us @ 50 MHz
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localparam integer DELAY_0_HIGH = 20 - 1; // 0.4 us @ 50 MHz
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localparam integer DELAY_0_LOW = 43 - 1; // 0.85 us @ 50 MHz
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localparam integer DELAY_RESET = 3000 - 1; // 60 us @ 50 MHz
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localparam RESET = 2'd0;
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localparam DATA_SEND = 2'd1;
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localparam BIT_SEND_HIGH = 2'd2;
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localparam BIT_SEND_LOW = 2'd3;
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reg [1:0] state = RESET;
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reg [8:0] bit_send = 0;
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reg [8:0] data_send = 0;
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reg [31:0] clk_count = 0;
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// Формат WS2812: обычно GRB, отправка старшим битом вперёд
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reg [23:0] WS2812_data = 24'h000001;
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always @(posedge CLOCK_50) begin
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case (state)
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RESET: begin
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WS2812 <= 1'b0;
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if (clk_count < DELAY_RESET)
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clk_count <= clk_count + 1'b1;
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else begin
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clk_count <= 0;
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// Смена цвета после передачи очередного кадра
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WS2812_data <= {WS2812_data[22:0], WS2812_data[23]};
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state <= DATA_SEND;
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end
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end
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DATA_SEND: begin
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if ((data_send == WS2812_NUM) &&
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(bit_send == WS2812_WIDTH)) begin
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data_send <= 0;
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bit_send <= 0;
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state <= RESET;
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end
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else if (bit_send < WS2812_WIDTH) begin
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state <= BIT_SEND_HIGH;
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end
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else begin
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data_send <= data_send + 1'b1;
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bit_send <= 0;
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state <= BIT_SEND_HIGH;
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end
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end
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BIT_SEND_HIGH: begin
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WS2812 <= 1'b1;
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if (WS2812_data[WS2812_WIDTH - 1 - bit_send]) begin
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if (clk_count < DELAY_1_HIGH)
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clk_count <= clk_count + 1'b1;
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else begin
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clk_count <= 0;
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state <= BIT_SEND_LOW;
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end
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end
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else begin
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if (clk_count < DELAY_0_HIGH)
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clk_count <= clk_count + 1'b1;
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else begin
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clk_count <= 0;
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state <= BIT_SEND_LOW;
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end
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end
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end
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BIT_SEND_LOW: begin
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WS2812 <= 1'b0;
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if (WS2812_data[WS2812_WIDTH - 1 - bit_send]) begin
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if (clk_count < DELAY_1_LOW)
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clk_count <= clk_count + 1'b1;
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else begin
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clk_count <= 0;
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bit_send <= bit_send + 1'b1;
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state <= DATA_SEND;
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end
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end
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else begin
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if (clk_count < DELAY_0_LOW)
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clk_count <= clk_count + 1'b1;
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else begin
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clk_count <= 0;
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bit_send <= bit_send + 1'b1;
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state <= DATA_SEND;
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end
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end
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end
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default: state <= RESET;
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endcase
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end
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endmodule |