101 lines
2.7 KiB
Verilog
101 lines
2.7 KiB
Verilog
module omdazz_WS2812b(
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input CLOCK_50,
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input [4:4] D_INP, // 3 (ADCHub1), 4 (ADCHub2) - используются
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output reg WS2812 // output interface to WS2812
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);
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parameter WS2812_NUM = 10 - 1 ; // number of WS2812 LEDs (1, counting from 0)
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parameter WS2812_WIDTH = 24 ; // WS2812 data bit width
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parameter CLK_FRE = 50_000_000;
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parameter F_SCALE = 50 / 27; // conversion factor from 27 MHz to 50 MHz
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parameter DELAY_1_HIGH = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1;
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parameter DELAY_1_LOW = (CLK_FRE / 1_000_000 * 40 / 100 * F_SCALE) - 1;
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parameter DELAY_0_HIGH = (CLK_FRE / 1_000_000 * 40 / 100 * F_SCALE) - 1;
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parameter DELAY_0_LOW = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1;
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parameter DELAY_RESET = (CLK_FRE / 10 * F_SCALE) - 1;
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parameter RESET = 0; // state machine declaration
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parameter DATA_SEND = 1;
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parameter BIT_SEND_HIGH = 2;
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parameter BIT_SEND_LOW = 3;
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reg [ 1:0] state = 0; // synthesis preserve // main state machine control
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reg [ 8:0] bit_send = 0; // amount of bits sent // increase it for larger LED strips/matrix
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reg [ 8:0] data_send = 0; // amount of data words sent // increase it for larger LED strips/matrix
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reg [31:0] clk_count = 0; // delay control
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reg [23:0] WS2812_data = 24'd1; // WS2812 color data
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always@(posedge CLOCK_50)
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case (state)
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RESET:begin
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WS2812 <= 0;
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if (clk_count < DELAY_RESET)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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WS2812_data <= {WS2812_data[22:0],WS2812_data[23]};// color shifting for cyclic
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state <= DATA_SEND;
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end
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end
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DATA_SEND:
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if (data_send == WS2812_NUM && bit_send == WS2812_WIDTH)begin
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data_send <= 0;
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bit_send <= 0;
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state <= RESET;
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end
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else if (bit_send < WS2812_WIDTH) begin
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state <= BIT_SEND_HIGH;
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end
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else begin// if (bit_send == WS2812_WIDTH)
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data_send <= data_send + 1;
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bit_send <= 0;
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state <= BIT_SEND_HIGH;
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end
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BIT_SEND_HIGH:begin
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WS2812 <= 1;
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if (WS2812_data[bit_send])
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if (clk_count < DELAY_1_HIGH)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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state <= BIT_SEND_LOW;
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end
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else
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if (clk_count < DELAY_0_HIGH)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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state <= BIT_SEND_LOW;
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end
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end
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BIT_SEND_LOW:begin
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WS2812 <= 0;
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if (WS2812_data[bit_send])
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if (clk_count < DELAY_1_LOW)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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bit_send <= bit_send + 1;
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state <= DATA_SEND;
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end
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else
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if (clk_count < DELAY_0_LOW)
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clk_count <= clk_count + 1;
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else begin
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clk_count <= 0;
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bit_send <= bit_send + 1;
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state <= DATA_SEND;
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end
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end
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endcase
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endmodule
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