From 4d0d51eefcbea027959c5bce59cbcd4550373519 Mon Sep 17 00:00:00 2001 From: pavel Date: Fri, 7 Aug 2026 17:30:49 +0300 Subject: [PATCH] files has been added --- omdazz_WS2812b.qpf | 30 ++++++++++++++ omdazz_WS2812b.qsf | 65 +++++++++++++++++++++++++++++ omdazz_WS2812b.v | 100 +++++++++++++++++++++++++++++++++++++++++++++ output_file.map | 11 +++++ 4 files changed, 206 insertions(+) create mode 100644 omdazz_WS2812b.qpf create mode 100644 omdazz_WS2812b.qsf create mode 100644 omdazz_WS2812b.v create mode 100644 output_file.map diff --git a/omdazz_WS2812b.qpf b/omdazz_WS2812b.qpf new file mode 100644 index 0000000..1ffe33f --- /dev/null +++ b/omdazz_WS2812b.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 17:00:54 August 07, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "17:00:54 August 07, 2026" + +# Revisions + +PROJECT_REVISION = "omdazz_WS2812b" diff --git a/omdazz_WS2812b.qsf b/omdazz_WS2812b.qsf new file mode 100644 index 0000000..a451a04 --- /dev/null +++ b/omdazz_WS2812b.qsf @@ -0,0 +1,65 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 17:00:54 August 07, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# omdazz_WS2812b_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE6E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY omdazz_WS2812b +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:00:54 AUGUST 07, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name SEARCH_PATH output_files/ +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE omdazz_WS2812b.v +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D_INP[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WS2812 +set_location_assignment PIN_23 -to CLOCK_50 +set_location_assignment PIN_31 -to D_INP[4] +set_location_assignment PIN_42 -to WS2812 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name CDF_FILE output_files/Chain1.cdf \ No newline at end of file diff --git a/omdazz_WS2812b.v b/omdazz_WS2812b.v new file mode 100644 index 0000000..7c38d63 --- /dev/null +++ b/omdazz_WS2812b.v @@ -0,0 +1,100 @@ +module omdazz_WS2812b( + input CLOCK_50, + input [4:4] D_INP, // 3 (ADCHub1), 4 (ADCHub2) - используются + output reg WS2812 // output interface to WS2812 +); + +parameter WS2812_NUM = 10 - 1 ; // number of WS2812 LEDs (1, counting from 0) +parameter WS2812_WIDTH = 24 ; // WS2812 data bit width +parameter CLK_FRE = 50_000_000; +parameter F_SCALE = 50 / 27; // conversion factor from 27 MHz to 50 MHz + +parameter DELAY_1_HIGH = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1; +parameter DELAY_1_LOW = (CLK_FRE / 1_000_000 * 40 / 100 * F_SCALE) - 1; +parameter DELAY_0_HIGH = (CLK_FRE / 1_000_000 * 40 / 100 * F_SCALE) - 1; +parameter DELAY_0_LOW = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1; +parameter DELAY_RESET = (CLK_FRE / 10 * F_SCALE) - 1; + +parameter RESET = 0; // state machine declaration +parameter DATA_SEND = 1; +parameter BIT_SEND_HIGH = 2; +parameter BIT_SEND_LOW = 3; + +reg [ 1:0] state = 0; // synthesis preserve // main state machine control +reg [ 8:0] bit_send = 0; // amount of bits sent // increase it for larger LED strips/matrix +reg [ 8:0] data_send = 0; // amount of data words sent // increase it for larger LED strips/matrix +reg [31:0] clk_count = 0; // delay control +reg [23:0] WS2812_data = 24'd1; // WS2812 color data + +always@(posedge CLOCK_50) + case (state) + RESET:begin + WS2812 <= 0; + + if (clk_count < DELAY_RESET) + clk_count <= clk_count + 1; + else begin + clk_count <= 0; + WS2812_data <= {WS2812_data[22:0],WS2812_data[23]};// color shifting for cyclic + state <= DATA_SEND; + end + end + + DATA_SEND: + if (data_send == WS2812_NUM && bit_send == WS2812_WIDTH)begin + data_send <= 0; + bit_send <= 0; + state <= RESET; + end + else if (bit_send < WS2812_WIDTH) begin + state <= BIT_SEND_HIGH; + end + else begin// if (bit_send == WS2812_WIDTH) + data_send <= data_send + 1; + bit_send <= 0; + state <= BIT_SEND_HIGH; + end + + BIT_SEND_HIGH:begin + WS2812 <= 1; + + if (WS2812_data[bit_send]) + if (clk_count < DELAY_1_HIGH) + clk_count <= clk_count + 1; + else begin + clk_count <= 0; + state <= BIT_SEND_LOW; + end + else + if (clk_count < DELAY_0_HIGH) + clk_count <= clk_count + 1; + else begin + clk_count <= 0; + state <= BIT_SEND_LOW; + end + end + + BIT_SEND_LOW:begin + WS2812 <= 0; + + if (WS2812_data[bit_send]) + if (clk_count < DELAY_1_LOW) + clk_count <= clk_count + 1; + else begin + clk_count <= 0; + + bit_send <= bit_send + 1; + state <= DATA_SEND; + end + else + if (clk_count < DELAY_0_LOW) + clk_count <= clk_count + 1; + else begin + clk_count <= 0; + + bit_send <= bit_send + 1; + state <= DATA_SEND; + end + end + endcase +endmodule diff --git a/output_file.map b/output_file.map new file mode 100644 index 0000000..571bb0b --- /dev/null +++ b/output_file.map @@ -0,0 +1,11 @@ +BLOCK START ADDRESS END ADDRESS + +Page_0 0x00000000 0x00059D8A + + + +Notes: + +- Data checksum for this conversion is 0x1A5EBC7A + +- All the addresses in this file are byte addresses \ No newline at end of file