pavel/Logic2_to_FPGA
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Author SHA1 Message Date
pavel
0cac4b916a create_clock -period 20 -name CLK50 [get_ports CLK50] 2026-06-01 06:39:06 +03:00
pavel
940920d18b added files 2026-06-01 06:19:27 +03:00
pavel
72ba761443 Initial commit 2026-06-01 04:16:43 +03:00