added stp2.stp
This commit is contained in:
parent
37f31f7dcb
commit
514814e555
@ -52,13 +52,13 @@ set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_location_assignment PIN_23 -to CLK50
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set_location_assignment PIN_23 -to CLK50
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set_location_assignment PIN_87 -to GPIO0
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set_location_assignment PIN_87 -to GPIO0
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set_location_assignment PIN_7 -to KEY0
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set_location_assignment PIN_88 -to KEY0
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY0
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY0
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@ -69,4 +69,40 @@ set_global_assignment -name VERILOG_FILE top.v
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set_global_assignment -name VERILOG_FILE pattern_rom.v
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set_global_assignment -name VERILOG_FILE pattern_rom.v
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set_global_assignment -name VERILOG_FILE pattern_player.v
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set_global_assignment -name VERILOG_FILE pattern_player.v
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set_instance_assignment -name SLEW_RATE 2 -to GPIO0
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set_instance_assignment -name SLEW_RATE 2 -to GPIO0
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
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set_global_assignment -name SIGNALTAP_FILE stp.stp
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set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to CLK50 -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
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set_global_assignment -name SIGNALTAP_FILE stp1.stp
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set_global_assignment -name SIGNALTAP_FILE stp2.stp
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=24" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
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set_location_assignment PIN_84 -to GPIO1
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to clk50_div2 -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to clk50_div2 -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT trigger_in -to clk50_div2 -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=44983" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=12698" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_FILE db/stp2_auto_stripped.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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22
output_file.cof
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22
output_file.cof
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@ -0,0 +1,22 @@
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<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
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<cof>
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<eprom_name>EPCS4</eprom_name>
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<flash_loader_device>EP4CE6</flash_loader_device>
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<output_filename>output_file.jic</output_filename>
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<n_pages>1</n_pages>
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<width>1</width>
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<mode>7</mode>
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<sof_data>
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<user_name>Page_0</user_name>
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<page_flags>1</page_flags>
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<bit0>
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<sof_filename>C:/Users/irobo/PycharmProjects/Logic2_to_FPGA/output_files/Logic2_to_FPGA.sof</sof_filename>
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</bit0>
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</sof_data>
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<version>5</version>
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<create_cvp_file>0</create_cvp_file>
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<auto_create_rpd>0</auto_create_rpd>
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<options>
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<map_file>1</map_file>
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</options>
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</cof>
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87
stp2.stp
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87
stp2.stp
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@ -0,0 +1,87 @@
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<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP3C(10|5)/EP4CE(10|6) (0x020F10DD)" sof_file="">
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<display_tree gui_logging_enabled="0">
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<display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
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</display_tree>
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<mnemonics/>
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<static_plugin_mnemonics/>
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<global_info>
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<single attribute="active instance" value="0"/>
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<single attribute="config widget visible" value="1"/>
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<single attribute="data log widget visible" value="1"/>
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<single attribute="hierarchy widget height" value="1"/>
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<single attribute="hierarchy widget visible" value="1"/>
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<single attribute="instance widget visible" value="1"/>
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<single attribute="jtag widget visible" value="1"/>
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<multi attribute="frame size" size="2" value="1024,705"/>
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<multi attribute="jtag widget size" size="2" value="334,135"/>
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</global_info>
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<instance entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
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<node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
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<position_info>
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<single attribute="active tab" value="1"/>
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</position_info>
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<signal_set global_temp="1" name="signal_set: 2026/06/01 21:17:43 #0">
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<clock name="CLK50" polarity="posedge" tap_mode="probeonly"/>
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<config is_hps_trigger_out_selected="false" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="yes" trigger_in_node="clk50_div2" trigger_in_tap_mode="probeonly" trigger_out_enable="no"/>
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<top_entity/>
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<signal_vec>
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<trigger_input_vec>
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<wire name="clk50_div2" tap_mode="probeonly"/>
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</trigger_input_vec>
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<data_input_vec>
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<wire name="clk50_div2" tap_mode="probeonly"/>
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</data_input_vec>
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<storage_qualifier_input_vec>
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<wire name="clk50_div2" tap_mode="probeonly"/>
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</storage_qualifier_input_vec>
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</signal_vec>
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<presentation>
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<unified_setup_data_view>
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<node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk50_div2" storage_index="0" tap_mode="probeonly" trigger_index="0" type="unknown"/>
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</unified_setup_data_view>
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<data_view>
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<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk50_div2" storage_index="0" tap_mode="probeonly" trigger_index="0" type="unknown"/>
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</data_view>
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<setup_view>
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<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk50_div2" storage_index="0" tap_mode="probeonly" trigger_index="0" type="unknown"/>
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</setup_view>
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<trigger_in_editor is_enabled="true" is_node_post_fitting="true" node_name="clk50_div2"/>
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<trigger_out_editor/>
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</presentation>
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<trigger attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2026/06/01 21:17:43 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="high" trigger_type="circular">
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<power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="high"/>
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<events use_custom_flow_control="no">
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<level enabled="yes" name="condition1" type="basic">
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<power_up enabled="yes">
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</power_up>
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<op_node/>
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</level>
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</events>
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<storage_qualifier_events>
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<transitional>1
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<pwr_up_transitional>1</pwr_up_transitional>
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</transitional>
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<storage_qualifier_level type="basic">
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<power_up>
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</power_up>
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<op_node/>
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</storage_qualifier_level>
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<storage_qualifier_level type="basic">
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<power_up>
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</power_up>
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<op_node/>
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</storage_qualifier_level>
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<storage_qualifier_level type="basic">
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<power_up>
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</power_up>
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<op_node/>
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</storage_qualifier_level>
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</storage_qualifier_events>
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<log>
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<data global_temp="1" name="log: 2026/06/01 21:17:43 #2"/>
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<extradata/>
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</log>
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</trigger>
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</signal_set>
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</instance>
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</session>
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28
top.v
28
top.v
@ -4,29 +4,35 @@
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module top (
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module top (
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input wire CLK50, // системный клок с платы (например, 50 МГц)
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input wire CLK50, // системный клок с платы (например, 50 МГц)
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input wire KEY0, // кнопка reset (на OMDAZZ часто активный низ)
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input wire KEY0, // кнопка reset (на OMDAZZ часто активный низ)
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output wire GPIO0 // выход на пин (оптопара/LED и т.п.)
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output wire GPIO0, // выход на пин (оптопара/LED и т.п.)
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output wire GPIO1 // ДОП. выход для clk50_div2 (подвесь на свободный пин)
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);
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);
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// ==========================
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// ==========================
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// Сброс (reset)
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// Сброс (reset)
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// ==========================
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// ==========================
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// Предположим, что KEY0 замыкает на 0, когда нажата → делаем rst = !KEY0.
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wire rst = ~KEY0;
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wire rst = ~KEY0;
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// ==========================
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// Делитель такта CLK50 / 2
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// ==========================
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reg clk50_div2 = 1'b0;
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always @(posedge CLK50 or posedge rst) begin
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if (rst)
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clk50_div2 <= 1'b0;
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else
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clk50_div2 <= ~clk50_div2;
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end
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// ==========================
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// ==========================
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// Сигнал запуска плеера
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// Сигнал запуска плеера
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// ==========================
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// ==========================
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// Для начала можем просто держать start = 1,
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// чтобы паттерн проигрывался один раз после сброса.
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// Если нужен запуск по кнопке — можно сделать простую логіку отдельно.
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wire start = 1'b1;
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wire start = 1'b1;
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// ==========================
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// ==========================
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// Параметры должны совпадать с pattern_rom.v
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// Параметры должны совпадать с pattern_rom.v
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// ==========================
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// ==========================
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localparam TICKS_WIDTH = 32;
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localparam TICKS_WIDTH = 32;
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// DEPTH возьми из комментария в созданном pattern_rom.v
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// (Python-скрипт его печатает). Например:
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localparam DEPTH = 128;
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localparam DEPTH = 128;
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// ==========================
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// ==========================
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@ -37,17 +43,17 @@ module top (
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pattern_player #(
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pattern_player #(
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.TICKS_WIDTH(TICKS_WIDTH),
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.TICKS_WIDTH(TICKS_WIDTH),
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.DEPTH(DEPTH)
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.DEPTH (DEPTH)
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) u_player (
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) u_player (
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.clk (CLK50), // тот же клок, что и в Python (F_CLK_HZ = 50e6)
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.clk (CLK50), // такт 50 МГц
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// если F_CLK_HZ другое — нужен PLL и другой сигнал clk
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.rst (rst),
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.rst (rst),
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.start (start),
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.start (start),
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.out (out_sig),
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.out (out_sig),
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.busy (busy)
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.busy (busy)
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);
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);
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// Выводим сигнал на внешний пин
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// Выводим сигнал плеера и делитель такта на внешние пины
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assign GPIO0 = out_sig;
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assign GPIO0 = out_sig;
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assign GPIO1 = clk50_div2; // сюда повесь светодиод или щуп
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endmodule
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endmodule
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Block a user