diff --git a/Logic2_to_FPGA.qsf b/Logic2_to_FPGA.qsf
index 13d0f54..c2f067d 100644
--- a/Logic2_to_FPGA.qsf
+++ b/Logic2_to_FPGA.qsf
@@ -52,13 +52,13 @@ set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_23 -to CLK50
set_location_assignment PIN_87 -to GPIO0
-set_location_assignment PIN_7 -to KEY0
+set_location_assignment PIN_88 -to KEY0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY0
@@ -69,4 +69,40 @@ set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_FILE pattern_rom.v
set_global_assignment -name VERILOG_FILE pattern_player.v
set_instance_assignment -name SLEW_RATE 2 -to GPIO0
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
+set_global_assignment -name SIGNALTAP_FILE stp.stp
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to CLK50 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SIGNALTAP_FILE stp1.stp
+set_global_assignment -name SIGNALTAP_FILE stp2.stp
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=24" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_location_assignment PIN_84 -to GPIO1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to clk50_div2 -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to clk50_div2 -section_id auto_signaltap_0
+set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT trigger_in -to clk50_div2 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=44983" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=12698" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_FILE db/stp2_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/output_file.cof b/output_file.cof
new file mode 100644
index 0000000..a9e3ebb
--- /dev/null
+++ b/output_file.cof
@@ -0,0 +1,22 @@
+
+
+ EPCS4
+ EP4CE6
+ output_file.jic
+ 1
+ 1
+ 7
+
+ Page_0
+ 1
+
+ C:/Users/irobo/PycharmProjects/Logic2_to_FPGA/output_files/Logic2_to_FPGA.sof
+
+
+ 5
+ 0
+ 0
+
+ 1
+
+
\ No newline at end of file
diff --git a/stp2.stp b/stp2.stp
new file mode 100644
index 0000000..6d4db68
--- /dev/null
+++ b/stp2.stp
@@ -0,0 +1,87 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/top.v b/top.v
index 23a0ce8..de8ee8a 100644
--- a/top.v
+++ b/top.v
@@ -4,30 +4,36 @@
module top (
input wire CLK50, // системный клок с платы (например, 50 МГц)
input wire KEY0, // кнопка reset (на OMDAZZ часто активный низ)
- output wire GPIO0 // выход на пин (оптопара/LED и т.п.)
+ output wire GPIO0, // выход на пин (оптопара/LED и т.п.)
+ output wire GPIO1 // ДОП. выход для clk50_div2 (подвесь на свободный пин)
);
// ==========================
// Сброс (reset)
// ==========================
- // Предположим, что KEY0 замыкает на 0, когда нажата → делаем rst = !KEY0.
wire rst = ~KEY0;
+ // ==========================
+ // Делитель такта CLK50 / 2
+ // ==========================
+ reg clk50_div2 = 1'b0;
+ always @(posedge CLK50 or posedge rst) begin
+ if (rst)
+ clk50_div2 <= 1'b0;
+ else
+ clk50_div2 <= ~clk50_div2;
+ end
+
// ==========================
// Сигнал запуска плеера
// ==========================
- // Для начала можем просто держать start = 1,
- // чтобы паттерн проигрывался один раз после сброса.
- // Если нужен запуск по кнопке — можно сделать простую логіку отдельно.
wire start = 1'b1;
// ==========================
// Параметры должны совпадать с pattern_rom.v
// ==========================
localparam TICKS_WIDTH = 32;
- // DEPTH возьми из комментария в созданном pattern_rom.v
- // (Python-скрипт его печатает). Например:
- localparam DEPTH = 128;
+ localparam DEPTH = 128;
// ==========================
// Соединения с pattern_player
@@ -37,17 +43,17 @@ module top (
pattern_player #(
.TICKS_WIDTH(TICKS_WIDTH),
- .DEPTH(DEPTH)
+ .DEPTH (DEPTH)
) u_player (
- .clk (CLK50), // тот же клок, что и в Python (F_CLK_HZ = 50e6)
- // если F_CLK_HZ другое — нужен PLL и другой сигнал clk
+ .clk (CLK50), // такт 50 МГц
.rst (rst),
.start (start),
.out (out_sig),
.busy (busy)
);
- // Выводим сигнал на внешний пин
+ // Выводим сигнал плеера и делитель такта на внешние пины
assign GPIO0 = out_sig;
+ assign GPIO1 = clk50_div2; // сюда повесь светодиод или щуп
endmodule
\ No newline at end of file