17 lines
334 B
Verilog
17 lines
334 B
Verilog
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module top(
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input wire CLOCK_50,
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input wire [4:4] D_INP,
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output wire WS2812_OUT
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);
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omdazz_WS2812b #(
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.WS2812_NUM(10 - 1),
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.CLK_FRE(50_000_000),
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.LED_MASK(10'b11_1111_1111) // LED0 и LED2
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) u_ws2812 (
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.CLOCK_50(CLOCK_50),
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.WS2812 (WS2812_OUT)
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);
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endmodule |