pavel/fblocks_Soloviev
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chapter1 #1

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pavel merged 4 commits from chapter1 into master 2026-07-11 00:28:57 +03:00
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5 changed files with 3829 additions and 5 deletions
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README.md
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@ -2,5 +2,8 @@
Этот репозиторий, чтобы изучать книгу Этот репозиторий, чтобы изучать книгу
Проектирование функциональных блоков встраиваемых систем на FPGA Проектирование функциональных блоков встраиваемых систем на FPGA
https://www.techbook.ru/book.php?id_book=1138 https://www.techbook.ru/book.php?id_book=1138
Для этого использую Altera Cyclone IV OMDAZZ (EP4CE6E22C8N),
а данные отправляю на пины с помощью esphome [can_pcf8574_bridge.yaml](https://giteadocker2.fvds.ru/pavel/fblocks_Soloviev/src/branch/master/esphome/can_pcf8574_bridge.yaml)

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TechMaps/Ch1/Ch1_single_port_ram_single_clk_v2.pdf Normal file
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5
chapter1.v
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//single_port_ram_single_clk //single_port_ram_single_clk_v2
module chapter1 module chapter1
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5) #(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5)
(input clk, we, (input clk, we,
@ -13,6 +13,7 @@ module chapter1
begin begin
if (we) if (we)
ram[address] <= data_in; //write ram[address] <= data_in; //write
data_out <= ram[address]; //read else
data_out <= ram[address]; //read
end end
endmodule endmodule

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fblocks.qsf
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@ -103,7 +103,5 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[0]
set_global_assignment -name VERILOG_FILE chapter1.v set_global_assignment -name VERILOG_FILE chapter1.v
set_global_assignment -name VERILOG_FILE blink.v
set_global_assignment -name SDC_FILE fblocks.sdc set_global_assignment -name SDC_FILE fblocks.sdc
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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output_file.cof
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<user_name>Page_0</user_name> <user_name>Page_0</user_name>
<page_flags>1</page_flags> <page_flags>1</page_flags>
<bit0> <bit0>
<sof_filename>C:/altera/13.1/FPGA/output_files/fblocks.sof</sof_filename> <sof_filename>C:/Users/pavel/PycharmProjects/fblocks_Soloviev/output_files/fblocks.sof</sof_filename>
</bit0> </bit0>
</sof_data> </sof_data>
<version>5</version> <version>5</version>