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chapter1 #1

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pavel merged 4 commits from chapter1 into master 2026-07-11 00:28:57 +03:00
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TechMaps/Ch1/Ch1_single_port_ram_single_clk_v2.pdf Normal file
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chapter1.v
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@ -1,4 +1,4 @@
//single_port_ram_single_clk //single_port_ram_single_clk_v2
module chapter1 module chapter1
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5) #(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5)
(input clk, we, (input clk, we,
@ -13,6 +13,7 @@ module chapter1
begin begin
if (we) if (we)
ram[address] <= data_in; //write ram[address] <= data_in; //write
else
data_out <= ram[address]; //read data_out <= ram[address]; //read
end end
endmodule endmodule