added files

2026-07-10 23:39:28 +03:00 · 2026-07-10 23:39:28 +03:00 · 4b820feec6
commit 4b820feec6
parent d2f4059eb3
13 changed files with 4179 additions and 0 deletions
--- a/.idea/fblocks_Soloviev.iml
+++ b/.idea/fblocks_Soloviev.iml
@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<module type="PYTHON_MODULE" version="4">
+  <component name="NewModuleRootManager">
+    <content url="file://$MODULE_DIR$" />
+    <orderEntry type="inheritedJdk" />
+    <orderEntry type="sourceFolder" forTests="false" />
+  </component>
+</module>
--- a/README.md
+++ b/README.md
@ -1,2 +1,6 @@
 # fblocks_Soloviev
+Этот репозиторий, чтобы изучать книгу
+Проектирование функциональных блоков встраиваемых систем на FPGA
+https://www.techbook.ru/book.php?id_book=1138
+

--- a/TechMaps/Ch1/Ch1_single_port_ram_single_clk.pdf
+++ b/TechMaps/Ch1/Ch1_single_port_ram_single_clk.pdf
--- a/books/Navabi_Z_per_s_angl_Soloveva_V_V__Proektirova_z-lib_org.pdf
+++ b/books/Navabi_Z_per_s_angl_Soloveva_V_V__Proektirova_z-lib_org.pdf
--- a/books/content_Soloviev.pdf
+++ b/books/content_Soloviev.pdf
--- a/chapter1.v
+++ b/chapter1.v
@ -0,0 +1,18 @@
+//single_port_ram_single_clk
+module chapter1
+		#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5)
+		(input clk, we,
+		input [DATA_WIDTH-1 : 0] data_in,
+		input [ADDR_WIDTH-1 : 0] address,
+		output reg [DATA_WIDTH-1 : 0] data_out);
+		
+		// declaring the memory matrix
+		reg [DATA_WIDTH-1 : 0] ram[2**ADDR_WIDTH-1 : 0];
+		
+		always @ (posedge clk)
+		begin
+				if (we)
+						ram[address] <= data_in; //write
+				data_out <= ram[address];		 //read
+		end		
+endmodule
--- a/esphome/can_pcf8574_bridge.yaml
+++ b/esphome/can_pcf8574_bridge.yaml
@ -0,0 +1,151 @@
+#esphome run can_pcf8574_bridge.yaml
+esphome:
+  name: can_pcf8574_bridge
+
+esp32:
+  board: nodemcu-32s
+  framework:
+    type: arduino
+
+logger:
+# Reference the secrets file from a directory above
+substitutions: !include ../secrets.yaml
+mqtt:
+  id: mqtt_client #MQTT id
+  broker: "${mqtt_broker}"
+  port: 1883
+  username: "${mqtt_username}"
+  password: "${mqtt_password}"
+ota:
+  platform: esphome
+  password: "${ota_password}"
+
+wifi:
+  networks:
+  - ssid: '${wifi_ssid1}'
+    password: '${wifi_password1}'
+  - ssid: '${wifi_ssid2}'
+    password: '${wifi_password2}'
+  - ssid: '${wifi_ssid3}'
+    password: '${wifi_password3}'
+  reboot_timeout: 60s
+  manual_ip:
+    # Set this to the IP of the ESP
+    static_ip: 192.168.xx.xx
+    # Set this to the IP address of the router. Often ends with .1
+    gateway: 192.168.xx.1
+    # The subnet of the network. 255.255.255.0 works for most home networks.
+    subnet: 255.255.255.0
+number:
+    - platform: template
+      name: "pcf_0x20"
+      optimistic: true
+      min_value: 0
+      max_value: 255
+      initial_value: 0
+      step: 1
+      mode: slider
+      id: id_pcf_0x20
+      icon: "mdi:counter"
+    - platform: template
+      name: "pcf_0x21"
+      optimistic: true
+      min_value: 0
+      max_value: 31
+      initial_value: 0
+      step: 1
+      mode: slider
+      id: id_pcf_0x21
+      icon: "mdi:counter"
+switch:
+    - platform: template
+      id: write_mode
+      name: "W"
+      optimistic: true
+spi:
+  - id: mcp_spi
+    clk_pin: GPIO18
+    mosi_pin: GPIO23
+    miso_pin: GPIO19
+
+i2c:
+  sda: GPIO21
+  scl: GPIO22
+  scan: true
+  id: bus_a
+
+pcf8574:
+  - id: pcf8574_0x20
+    address: 0x20
+    pcf8575: false
+  - id: pcf8574_0x21
+    address: 0x21
+    pcf8575: false
+
+interval:
+  - interval: 100ms
+    then:
+      - lambda: |-
+          uint8_t pcf_0x20 = (uint8_t)id(id_pcf_0x20).state;
+          uint8_t pcf_0x21 = (uint8_t)id(id_pcf_0x21).state;
+          bool    is_write    = id(write_mode).state;
+          uint8_t base   = pcf_0x21 & 0x1F;
+          uint8_t result = (base & ~0x80) | (is_write ? 0x80 : 0x00);
+          id(bus_a).write(0x20, &pcf_0x20, 1);
+          ESP_LOGI("i2c pcf_0x20", "Sent: 0x%02X", pcf_0x20);
+          id(bus_a).write(0x21, &result, 1);
+          ESP_LOGI("i2c pcf_0x21", "Sent: 0x%02X", result);
+          char bin[9];
+          for (int i = 7; i >= 0; --i) {
+              bin[7 - i] = (result & (1 << i)) ? '1' : '0';
+          }
+          bin[8] = '\0';
+          ESP_LOGI("i2c", "Sent: %s", bin);
+ 
+
+canbus:
+  - platform: mcp2515
+    spi_id: mcp_spi
+    cs_pin: GPIO5
+    can_id: 4
+    use_extended_id: false
+    bit_rate: 500kbps
+    id: mcp2515_bus
+    on_frame:
+      - can_id: 0
+        can_id_mask: 0
+        use_extended_id: false
+        remote_transmission_request: false
+        then:
+          - lambda: |-
+              bool ext = false;
+              auto pdo_id = can_id;
+
+              if (pdo_id == 0x150) {
+                if (x[0] == 0x01) {
+                  // обработка запуска
+                }
+                if (x[0] == 0x00) {
+                  // обработка остановки
+                }
+              }
+
+              if (pdo_id >= 0x160 && pdo_id <= 0x18F) {
+                uint8_t node_id = pdo_id - 0x160 + 1;
+
+                if (x[0] == 0x01) {
+                  // индивидуальный запуск
+                }
+                if (x[0] == 0x00) {
+                  // индивидуальная остановка
+                }
+
+                uint64_t I = (uint64_t)(x[2] << 8) | x[1];
+                uint64_t I_ma = I * 1000 * 0.0146628;
+                uint8_t byte1 = (I_ma >> 24) & 0xFF;
+                uint8_t byte2 = (I_ma >> 16) & 0xFF;
+                uint8_t byte3 = (I_ma >> 8)  & 0xFF;
+                uint8_t byte4 =  I_ma        & 0xFF;
+
+                // использование I_ma по твоей логике
+              }
--- a/fblocks.qpf
+++ b/fblocks.qpf
@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 22:01:46  July 08, 2026
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "22:01:46  July 08, 2026"
+
+# Revisions
+
+PROJECT_REVISION = "fblocks"
--- a/fblocks.qsf
+++ b/fblocks.qsf
@ -0,0 +1,109 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 22:01:46  July 08, 2026
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		fblocks_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE6E22C8
+set_global_assignment -name TOP_LEVEL_ENTITY chapter1
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:01:46  JULY 08, 2026"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_23 -to clk
+set_location_assignment PIN_87 -to led
+set_location_assignment PIN_138 -to data_in[0]
+set_location_assignment PIN_141 -to data_in[1]
+set_location_assignment PIN_137 -to data_in[2]
+set_location_assignment PIN_136 -to data_in[3]
+set_location_assignment PIN_135 -to data_in[4]
+set_location_assignment PIN_133 -to data_in[5]
+set_location_assignment PIN_132 -to data_in[6]
+set_location_assignment PIN_129 -to data_in[7]
+set_location_assignment PIN_30 -to address[0]
+set_location_assignment PIN_32 -to address[1]
+set_location_assignment PIN_34 -to address[2]
+set_location_assignment PIN_39 -to address[3]
+set_location_assignment PIN_43 -to address[4]
+set_location_assignment PIN_52 -to we
+set_location_assignment PIN_119 -to data_out[0]
+set_location_assignment PIN_121 -to data_out[1]
+set_location_assignment PIN_126 -to data_out[2]
+set_location_assignment PIN_124 -to data_out[3]
+set_location_assignment PIN_120 -to data_out[4]
+set_location_assignment PIN_115 -to data_out[5]
+set_location_assignment PIN_113 -to data_out[6]
+set_location_assignment PIN_111 -to data_out[7]
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to we
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[0]
+set_global_assignment -name VERILOG_FILE chapter1.v
+set_global_assignment -name VERILOG_FILE blink.v
+set_global_assignment -name SDC_FILE fblocks.sdc
+set_global_assignment -name CDF_FILE output_files/Chain1.cdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/fblocks.sdc
+++ b/fblocks.sdc
@ -0,0 +1,4 @@
+create_clock -period 20 -name clk [get_ports clk]
+set_false_path -from [all_clocks] -to [get_ports {led}]
+
+
--- a/output_file.cof
+++ b/output_file.cof
@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
+<cof>
+	<eprom_name>EPCS16</eprom_name>
+	<flash_loader_device>EP4CE6</flash_loader_device>
+	<output_filename>output_file.jic</output_filename>
+	<n_pages>1</n_pages>
+	<width>1</width>
+	<mode>7</mode>
+	<sof_data>
+		<user_name>Page_0</user_name>
+		<page_flags>1</page_flags>
+		<bit0>
+			<sof_filename>C:/altera/13.1/FPGA/output_files/fblocks.sof</sof_filename>
+		</bit0>
+	</sof_data>
+	<version>5</version>
+	<create_cvp_file>0</create_cvp_file>
+	<auto_create_rpd>0</auto_create_rpd>
+	<options>
+		<map_file>1</map_file>
+	</options>
+</cof>
--- a/output_file.jic
+++ b/output_file.jic
--- a/output_file.map
+++ b/output_file.map
@ -0,0 +1,11 @@
+BLOCK		START ADDRESS		END ADDRESS
+
+Page_0		0x00000000		0x00059D8A
+
+
+
+Notes:
+
+- Data checksum for this conversion is 0x1A5DF032
+
+- All the addresses in this file are byte addresses