18 lines
460 B
Verilog
18 lines
460 B
Verilog
//single_port_ram_single_clk
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module chapter1
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#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5)
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(input clk, we,
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input [DATA_WIDTH-1 : 0] data_in,
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input [ADDR_WIDTH-1 : 0] address,
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output reg [DATA_WIDTH-1 : 0] data_out);
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// declaring the memory matrix
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reg [DATA_WIDTH-1 : 0] ram[2**ADDR_WIDTH-1 : 0];
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always @ (posedge clk)
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begin
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if (we)
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ram[address] <= data_in; //write
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data_out <= ram[address]; //read
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end
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endmodule |