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changed chapter1.v

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single_port_ram_single_clk_v2
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pavel 2026-07-11 00:05:38 +03:00
parent e9f73557f4
commit 11424be3d3
2 changed files with 3825 additions and 2 deletions
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TechMaps/Ch1/Ch1_single_port_ram_single_clk_v2.pdf Normal file
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chapter1.v
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@ -1,4 +1,4 @@
//single_port_ram_single_clk
//single_port_ram_single_clk_v2
module chapter1
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5)
(input clk, we,
@ -13,6 +13,7 @@ module chapter1
begin
if (we)
ram[address] <= data_in; //write
data_out <= ram[address]; //read
else
data_out <= ram[address]; //read
end
endmodule