pavel/Logic2_to_FPGA
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create_clock -period 20 -name CLK50 [get_ports CLK50]

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pavel 2026-06-01 06:39:06 +03:00
parent 940920d18b
commit 0cac4b916a
2 changed files with 4 additions and 3 deletions
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5
Logic2_to_FPGA.qsf
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@ -62,10 +62,11 @@ set_location_assignment PIN_7 -to KEY0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SOURCE_FILE Logic2_to_FPGA.qpf
set_global_assignment -name SOURCE_FILE Logic2_to_FPGA.qsf
set_global_assignment -name SDC_FILE omdazz.sdc
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_FILE pattern_rom.v
set_global_assignment -name VERILOG_FILE pattern_player.v
set_global_assignment -name VERILOG_FILE pattern_player.v
set_instance_assignment -name SLEW_RATE 2 -to GPIO0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
omdazz.sdc
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@ -1,3 +1,3 @@
create_clock -period 20 -name clk [get_ports clk]
create_clock -period 20.0 -name CLK50 [get_ports CLK50]