diff --git a/Logic2_to_FPGA.qsf b/Logic2_to_FPGA.qsf
index c2ea0d7..13d0f54 100644
--- a/Logic2_to_FPGA.qsf
+++ b/Logic2_to_FPGA.qsf
@@ -62,10 +62,11 @@ set_location_assignment PIN_7 -to KEY0
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY0
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name SOURCE_FILE Logic2_to_FPGA.qpf
 set_global_assignment -name SOURCE_FILE Logic2_to_FPGA.qsf
 set_global_assignment -name SDC_FILE omdazz.sdc
 set_global_assignment -name VERILOG_FILE top.v
 set_global_assignment -name VERILOG_FILE pattern_rom.v
-set_global_assignment -name VERILOG_FILE pattern_player.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE pattern_player.v
+set_instance_assignment -name SLEW_RATE 2 -to GPIO0
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/omdazz.sdc b/omdazz.sdc
index 29cb6da..58c7d33 100644
--- a/omdazz.sdc
+++ b/omdazz.sdc
@@ -1,3 +1,3 @@
-create_clock -period 20 -name clk [get_ports clk]
+create_clock -period 20.0 -name CLK50 [get_ports CLK50]