pavel
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  • Joined on 2026-03-30
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8
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1
pavel pushed to main_UNIT2 at pavel/FOEXP_T 2026-06-12 23:32:13 +03:00
739275e71c added oldbooster pictures
pavel pushed to main_UNIT2 at pavel/FOEXP_T 2026-06-12 23:29:36 +03:00
836e69ede0 added oldbooster.jpg
pavel pushed to main_UNIT2 at pavel/FOEXP_T 2026-06-12 23:27:50 +03:00
c6555ee515 added branch main_UNIT2
pavel created branch main_UNIT2 in pavel/FOEXP_T 2026-06-12 23:15:25 +03:00
pavel pushed to main_UNIT2 at pavel/FOEXP_T 2026-06-12 23:15:25 +03:00
234f560f2c added branch main_UNIT2
pavel pushed to main at pavel/FOEXP_T 2026-06-12 22:42:39 +03:00
e08d94509f added FOExp.qar
pavel pushed to master at pavel/FOEXP_T_ALL 2026-06-12 15:54:18 +03:00
e01f747b38 edited README.md
pavel pushed to master at pavel/FOEXP_T_ALL 2026-06-12 15:20:10 +03:00
a30bdf69f3 assign SKiiP_EN = 4'b0000;
pavel pushed to debug at pavel/FOEXP_T_ALL 2026-06-12 00:23:23 +03:00
76262323af output [4:1] SKiiP_EN_DBG;
pavel created branch debug in pavel/FOEXP_T_ALL 2026-06-12 00:23:23 +03:00
pavel pushed to master at pavel/FOEXP_T_ALL 2026-06-11 19:43:28 +03:00
6ed9f4dcc2 assign SKiiP_CTRL = 4'b1111;
pavel created branch master in pavel/FOEXP_T_ALL 2026-06-11 19:43:28 +03:00
pavel pushed to main at pavel/FOEXP_T_ALL 2026-06-11 19:30:09 +03:00
1fc237d550 added files
pavel created repository pavel/FOEXP_T_ALL 2026-06-11 19:21:20 +03:00
pavel pushed to master at pavel/Logic2_to_FPGA 2026-06-02 01:16:22 +03:00
6c2ec790a7 added схема платы плис V2.5.pdf
pavel pushed to master at pavel/Logic2_to_FPGA 2026-06-02 01:14:37 +03:00
0d5e47f74a added error.txt
pavel pushed to master at pavel/Logic2_to_FPGA 2026-06-02 00:51:01 +03:00
514814e555 added stp2.stp
pavel pushed to master at pavel/Logic2_to_FPGA 2026-06-01 19:41:34 +03:00
37f31f7dcb added real data
pavel pushed to master at pavel/Logic2_to_FPGA 2026-06-01 17:39:48 +03:00
5ec983c2bd added digital.csv
pavel pushed to master at pavel/Logic2_to_FPGA 2026-06-01 06:38:38 +03:00
0cac4b916a create_clock -period 20 -name CLK50 [get_ports CLK50]