16 lines
296 B
Verilog
16 lines
296 B
Verilog
//top module
|
|
module top(
|
|
input wire CLOCK_50,
|
|
input wire [4:4] D_INP,
|
|
output wire WS2812_OUT
|
|
);
|
|
|
|
omdazz_WS2812b #(
|
|
.WS2812_NUM(10 - 1),
|
|
.CLK_FRE(50_000_000)
|
|
) u_ws2812 (
|
|
.CLOCK_50(CLOCK_50),
|
|
.WS2812 (WS2812_OUT)
|
|
);
|
|
|
|
endmodule |