pavel/omdazz_WS2812b
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master1 #2

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pavel merged 5 commits from master1 into master 2026-08-07 19:09:34 +03:00
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3 changed files with 22 additions and 16 deletions
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20
omdazz_WS2812b.qsf
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@ -38,7 +38,7 @@
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY omdazz_WS2812b
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:00:54 AUGUST 07, 2026"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
@ -48,18 +48,20 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name VERILOG_FILE omdazz_WS2812b.v
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D_INP[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WS2812
set_location_assignment PIN_23 -to CLOCK_50
set_location_assignment PIN_31 -to D_INP[4]
set_location_assignment PIN_42 -to WS2812
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name SDC_FILE omdazz_WS2812b.sdc
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_FILE omdazz_WS2812b.v
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_42 -to WS2812_OUT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WS2812_OUT
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

3
omdazz_WS2812b.sdc Normal file
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@ -0,0 +1,3 @@
create_clock -period 20 -name CLOCK_50 [get_ports CLOCK_50]

15
omdazz_WS2812b.v
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@ -1,12 +1,13 @@
module omdazz_WS2812b(
input CLOCK_50,
input [4:4] D_INP, // 3 (ADCHub1), 4 (ADCHub2) - используются
output reg WS2812 // output interface to WS2812
module omdazz_WS2812b #(
parameter integer WS2812_NUM = 10 - 1,
parameter integer WS2812_WIDTH = 24,
parameter integer CLK_FRE = 50_000_000
)(
input wire CLOCK_50,
output reg WS2812
);
parameter WS2812_NUM = 10 - 1 ; // number of WS2812 LEDs (1, counting from 0)
parameter WS2812_WIDTH = 24 ; // WS2812 data bit width
parameter CLK_FRE = 50_000_000;
parameter F_SCALE = 50 / 27; // conversion factor from 27 MHz to 50 MHz
parameter DELAY_1_HIGH = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1;