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pavel 2026-08-07 19:20:33 +03:00
parent e68f569ee2
commit e509bcd442
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top.v
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@ -1,4 +1,4 @@
//top module top module
module top( module top(
input wire CLOCK_50, input wire CLOCK_50,
input wire [4:4] D_INP, input wire [4:4] D_INP,