From cd96a065b8812ffcc5055ec0a8179d804fb20bcd Mon Sep 17 00:00:00 2001
From: pavel <pav9551@yandex.ru>
Date: Fri, 7 Aug 2026 20:24:04 +0300
Subject: [PATCH] added led_mask

---
 omdazz_WS2812b.v | 11 ++++++++---
 output_file.map  |  2 +-
 top.v            |  5 +++--
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/omdazz_WS2812b.v b/omdazz_WS2812b.v
index b6a83cd..1744827 100644
--- a/omdazz_WS2812b.v
+++ b/omdazz_WS2812b.v
@@ -1,7 +1,8 @@
 module omdazz_WS2812b #(
     parameter integer WS2812_NUM   = 10 - 1,
     parameter integer WS2812_WIDTH = 24,
-    parameter integer CLK_FRE      = 50_000_000
+    parameter integer CLK_FRE      = 50_000_000,
+	 parameter [WS2812_NUM:0] LED_MASK 
 )(
     input  wire CLOCK_50,
     output reg  WS2812
@@ -27,6 +28,10 @@ reg [ 8:0] data_send   = 0; // amount of data words sent // increase it for larg
 reg [31:0] clk_count   = 0; // delay control
 reg [23:0] WS2812_data = 24'd1; // WS2812 color data
 
+wire send_bit;
+assign send_bit = WS2812_data[bit_send] & LED_MASK[data_send];
+//assign send_bit = (data_send == 0) ? WS2812_data[bit_send] : 1'b0;
+
 always@(posedge CLOCK_50)
 	case (state)
 		RESET:begin
@@ -59,7 +64,7 @@ always@(posedge CLOCK_50)
 		BIT_SEND_HIGH:begin
 			WS2812 <= 1;
 
-			if (WS2812_data[bit_send]) 
+			if (send_bit) 
 				if (clk_count < DELAY_1_HIGH)
 					clk_count <= clk_count + 1;
 				else begin
@@ -78,7 +83,7 @@ always@(posedge CLOCK_50)
 		BIT_SEND_LOW:begin
 			WS2812 <= 0;
 
-			if (WS2812_data[bit_send]) 
+			if (send_bit) 
 				if (clk_count < DELAY_1_LOW) 
 					clk_count <= clk_count + 1;
 				else begin
diff --git a/output_file.map b/output_file.map
index 571bb0b..4cc6789 100644
--- a/output_file.map
+++ b/output_file.map
@@ -6,6 +6,6 @@ Page_0		0x00000000		0x00059D8A
 
 Notes:
 
-- Data checksum for this conversion is 0x1A5EBC7A
+- Data checksum for this conversion is 0x1A5DDC5D
 
 - All the addresses in this file are byte addresses
\ No newline at end of file
diff --git a/top.v b/top.v
index 545aef3..2dc37fe 100644
--- a/top.v
+++ b/top.v
@@ -1,4 +1,4 @@
-//top module
+
 module top(
     input  wire       CLOCK_50,
     input  wire [4:4] D_INP,
@@ -7,7 +7,8 @@ module top(
 
     omdazz_WS2812b #(
         .WS2812_NUM(10 - 1),
-        .CLK_FRE(50_000_000)
+        .CLK_FRE(50_000_000),
+		  .LED_MASK(10'b11_1111_1111)  // LED0 и LED2
     ) u_ws2812 (
         .CLOCK_50(CLOCK_50),
         .WS2812  (WS2812_OUT)