From 7541a0439d7c4b2c13e976b35331536392d17f39 Mon Sep 17 00:00:00 2001 From: pavel Date: Fri, 7 Aug 2026 19:09:19 +0300 Subject: [PATCH 1/4] driver WS2812b moved to the other module --- omdazz_WS2812b.qsf | 20 +++++++++++--------- omdazz_WS2812b.sdc | 3 +++ omdazz_WS2812b.v | 15 ++++++++------- 3 files changed, 22 insertions(+), 16 deletions(-) create mode 100644 omdazz_WS2812b.sdc diff --git a/omdazz_WS2812b.qsf b/omdazz_WS2812b.qsf index a451a04..677dfb6 100644 --- a/omdazz_WS2812b.qsf +++ b/omdazz_WS2812b.qsf @@ -38,7 +38,7 @@ set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE6E22C8 -set_global_assignment -name TOP_LEVEL_ENTITY omdazz_WS2812b +set_global_assignment -name TOP_LEVEL_ENTITY top set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:00:54 AUGUST 07, 2026" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" @@ -48,18 +48,20 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name VERILOG_FILE omdazz_WS2812b.v set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D_INP[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WS2812 set_location_assignment PIN_23 -to CLOCK_50 set_location_assignment PIN_31 -to D_INP[4] -set_location_assignment PIN_42 -to WS2812 -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name CDF_FILE output_files/Chain1.cdf \ No newline at end of file +set_global_assignment -name SDC_FILE omdazz_WS2812b.sdc +set_global_assignment -name VERILOG_FILE top.v +set_global_assignment -name VERILOG_FILE omdazz_WS2812b.v +set_global_assignment -name CDF_FILE output_files/Chain1.cdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_42 -to WS2812_OUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to WS2812_OUT +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/omdazz_WS2812b.sdc b/omdazz_WS2812b.sdc new file mode 100644 index 0000000..fc7063b --- /dev/null +++ b/omdazz_WS2812b.sdc @@ -0,0 +1,3 @@ +create_clock -period 20 -name CLOCK_50 [get_ports CLOCK_50] + + diff --git a/omdazz_WS2812b.v b/omdazz_WS2812b.v index 7c38d63..b6a83cd 100644 --- a/omdazz_WS2812b.v +++ b/omdazz_WS2812b.v @@ -1,12 +1,13 @@ -module omdazz_WS2812b( - input CLOCK_50, - input [4:4] D_INP, // 3 (ADCHub1), 4 (ADCHub2) - используются - output reg WS2812 // output interface to WS2812 +module omdazz_WS2812b #( + parameter integer WS2812_NUM = 10 - 1, + parameter integer WS2812_WIDTH = 24, + parameter integer CLK_FRE = 50_000_000 +)( + input wire CLOCK_50, + output reg WS2812 ); -parameter WS2812_NUM = 10 - 1 ; // number of WS2812 LEDs (1, counting from 0) -parameter WS2812_WIDTH = 24 ; // WS2812 data bit width -parameter CLK_FRE = 50_000_000; + parameter F_SCALE = 50 / 27; // conversion factor from 27 MHz to 50 MHz parameter DELAY_1_HIGH = (CLK_FRE / 1_000_000 * 85 / 100 * F_SCALE) - 1; From 3abb632ceef4b8ffc6187def1c0e59224a2596c1 Mon Sep 17 00:00:00 2001 From: pavel Date: Fri, 7 Aug 2026 19:10:07 +0300 Subject: [PATCH 2/4] top.v has been added --- top.v | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 top.v diff --git a/top.v b/top.v new file mode 100644 index 0000000..491b265 --- /dev/null +++ b/top.v @@ -0,0 +1,15 @@ +module top( + input wire CLOCK_50, + input wire [4:4] D_INP, + output wire WS2812_OUT +); + + omdazz_WS2812b #( + .WS2812_NUM(10 - 1), + .CLK_FRE(50_000_000) + ) u_ws2812 ( + .CLOCK_50(CLOCK_50), + .WS2812 (WS2812_OUT) + ); + +endmodule \ No newline at end of file From 3aa5e6bfac7ac9c54a0f11ead55b62c3de8b97f8 Mon Sep 17 00:00:00 2001 From: pavel Date: Fri, 7 Aug 2026 19:15:17 +0300 Subject: [PATCH 3/4] top.v has been added --- top.v | 1 + 1 file changed, 1 insertion(+) diff --git a/top.v b/top.v index 491b265..545aef3 100644 --- a/top.v +++ b/top.v @@ -1,3 +1,4 @@ +//top module module top( input wire CLOCK_50, input wire [4:4] D_INP, From e509bcd4423e773583f7afc9e9f66242763aae0a Mon Sep 17 00:00:00 2001 From: pavel Date: Fri, 7 Aug 2026 19:20:33 +0300 Subject: [PATCH 4/4] top.v has been added --- top.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/top.v b/top.v index 545aef3..76e314f 100644 --- a/top.v +++ b/top.v @@ -1,4 +1,4 @@ -//top module +top module module top( input wire CLOCK_50, input wire [4:4] D_INP,