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pavel 2026-08-07 19:15:17 +03:00
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commit 3aa5e6bfac
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top.v
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@ -1,3 +1,4 @@
//top module
module top( module top(
input wire CLOCK_50, input wire CLOCK_50,
input wire [4:4] D_INP, input wire [4:4] D_INP,