# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 22:01:46  July 08, 2026
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		fblocks_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY chapter1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:01:46  JULY 08, 2026"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_23 -to clk
set_location_assignment PIN_87 -to led
set_location_assignment PIN_138 -to data_in[0]
set_location_assignment PIN_141 -to data_in[1]
set_location_assignment PIN_137 -to data_in[2]
set_location_assignment PIN_136 -to data_in[3]
set_location_assignment PIN_135 -to data_in[4]
set_location_assignment PIN_133 -to data_in[5]
set_location_assignment PIN_132 -to data_in[6]
set_location_assignment PIN_129 -to data_in[7]
set_location_assignment PIN_30 -to address[0]
set_location_assignment PIN_32 -to address[1]
set_location_assignment PIN_34 -to address[2]
set_location_assignment PIN_39 -to address[3]
set_location_assignment PIN_43 -to address[4]
set_location_assignment PIN_52 -to we
set_location_assignment PIN_119 -to data_out[0]
set_location_assignment PIN_121 -to data_out[1]
set_location_assignment PIN_126 -to data_out[2]
set_location_assignment PIN_124 -to data_out[3]
set_location_assignment PIN_120 -to data_out[4]
set_location_assignment PIN_115 -to data_out[5]
set_location_assignment PIN_113 -to data_out[6]
set_location_assignment PIN_111 -to data_out[7]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to address[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_in[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to we
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to data_out[0]
set_global_assignment -name VERILOG_FILE chapter1.v
set_global_assignment -name SDC_FILE fblocks.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top