//single_port_ram_single_clk_v2
module chapter1
		#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5)
		(input clk, we,
		input [DATA_WIDTH-1 : 0] data_in,
		input [ADDR_WIDTH-1 : 0] address,
		output reg [DATA_WIDTH-1 : 0] data_out);
		
		// declaring the memory matrix
		reg [DATA_WIDTH-1 : 0] ram[2**ADDR_WIDTH-1 : 0];
		
		always @ (posedge clk)
		begin
				if (we)
						ram[address] <= data_in; //write
				else
						data_out <= ram[address];		 //read
		end		
endmodule