22 lines
360 B
Verilog
22 lines
360 B
Verilog
module blink(
|
|
input clk,
|
|
output reg led
|
|
);
|
|
|
|
localparam MAX_COUNT = 50_000_000 - 1; // для 50 MHz → ~1 секунда
|
|
|
|
reg [26:0] cnt;// 2^26 = 67_108_864
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if(cnt >= MAX_COUNT)
|
|
begin
|
|
cnt <= 0;
|
|
led <= ~led; // переключение LED
|
|
end
|
|
else
|
|
cnt <= cnt + 1;
|
|
end
|
|
|
|
endmodule
|