103 lines
3.4 KiB
Verilog
103 lines
3.4 KiB
Verilog
module blink #(
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// Input clock frequency in Hz
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parameter integer F_CLK = 50_000_000 // 50 MHz
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)(
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input wire clk,
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output wire led,
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output wire pin,
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output wire pin_10
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);
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//---------------------------------------------------------
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// Step duration:
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// - for 0 Hz : 8 s
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// - for others : 4 s
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//---------------------------------------------------------
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localparam integer STEP_4SEC_MAX = (F_CLK * 4) - 1;
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localparam integer STEP_8SEC_MAX = (F_CLK * 8) - 1;
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// Step timer counter
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reg [31:0] step_cnt = 32'd0;
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// Frequency index: 0..5 → 0,10,20,30,40,50 Hz
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reg [2:0] freq_idx = 3'd0;
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// Half-period counter and current half-period length in clock cycles
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reg [31:0] blink_cnt = 32'd0;
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reg [31:0] max_count = 32'd0;
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// Base LED signal (before output inversions)
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reg led_base = 1'b0;
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//---------------------------------------------------------
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// Function to calculate half-period in clock cycles
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//---------------------------------------------------------
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function [31:0] calc_max_count;
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input [2:0] idx;
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integer f;
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begin
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// Frequency in Hz: 0, 10, 20, 30, 40, 50
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f = idx * 10;
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if (f == 0) begin
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// Special case: 0 Hz → no blinking
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calc_max_count = 32'd0;
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end else begin
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// Half-period: F_CLK / (2 * f)
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calc_max_count = (F_CLK / (2 * f)) - 1;
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end
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end
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endfunction
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//---------------------------------------------------------
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// Main process: step timing, frequency selection,
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// blink generation
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//---------------------------------------------------------
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always @(posedge clk) begin
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//-----------------------------------------------------
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// Step timer: change frequency every 4 or 8 seconds
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//-----------------------------------------------------
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if (step_cnt >= (freq_idx == 3'd0 ? STEP_8SEC_MAX : STEP_4SEC_MAX)) begin
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step_cnt <= 32'd0;
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// Cycle through 0→1→2→3→4→5→0...
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if (freq_idx == 3'd5)
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freq_idx <= 3'd0;
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else
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freq_idx <= freq_idx + 3'd1;
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end else begin
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step_cnt <= step_cnt + 32'd1;
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end
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//-----------------------------------------------------
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// Recalculate half-period for current frequency
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//-----------------------------------------------------
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max_count <= calc_max_count(freq_idx);
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//-----------------------------------------------------
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// Blink generation
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//-----------------------------------------------------
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if (max_count == 32'd0) begin
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// 0 Hz: hold current state, no blinking
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blink_cnt <= 32'd0;
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// led_base keeps its last value
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end else begin
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if (blink_cnt >= max_count) begin
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blink_cnt <= 32'd0;
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led_base <= ~led_base;
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end else begin
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blink_cnt <= blink_cnt + 32'd1;
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end
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end
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end
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//---------------------------------------------------------
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// Outputs:
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// led = inverted base signal
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// pin = same as led
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// pin_10 = inverted pin
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//---------------------------------------------------------
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assign led = ~led_base;
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assign pin = led;
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assign pin_10 = ~pin;
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endmodule |