44 lines
612 B
Verilog
44 lines
612 B
Verilog
`timescale 1ns/1ps
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module tb_blink;
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reg clk;
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wire led;
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blink DUT(
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.clk(clk),
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.led(led)
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);
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// Clock generator (50 MHz)
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always #10 clk = ~clk;
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// Self checking logic
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integer error_count = 0;
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reg led_prev;
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initial begin
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clk = 0;
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led_prev = 0;
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#100000; // simulate time
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if(error_count == 0)
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$display("SELF CHECK PASSED");
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else
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$display("SELF CHECK FAILED, errors = %d", error_count);
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$stop;
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end
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// Check LED toggle behavior
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always @(posedge clk)
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begin
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#1;
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if(led == led_prev)
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error_count = error_count + 1;
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led_prev = led;
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end
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endmodule |