diff --git a/.gitignore b/.gitignore index 0a945a5..5d57660 100644 --- a/.gitignore +++ b/.gitignore @@ -105,3 +105,30 @@ hw_handoff ipshared +# Временные папки Quartus +db/ +incremental_db/ +greybox_tmp/ +hc_output/ +hps_isw_software/ +simulation/ +output_files/ + +# Промежуточные файлы +*.bak +*.orig +*.rpt +*.summary +*.qws +*.jdi +*.pin +*.done +*.qdf +*.sld + +# Прошивки (если не нужны в репозитории) +*.sof +*.pof +*.jic + + diff --git a/.idea/.gitignore b/.idea/.gitignore new file mode 100644 index 0000000..30cf57e --- /dev/null +++ b/.idea/.gitignore @@ -0,0 +1,10 @@ +# Default ignored files +/shelf/ +/workspace.xml +# Editor-based HTTP Client requests +/httpRequests/ +# Ignored default folder with query files +/queries/ +# Datasource local storage ignored files +/dataSources/ +/dataSources.local.xml diff --git a/.idea/Quartus_blink.iml b/.idea/Quartus_blink.iml new file mode 100644 index 0000000..d0876a7 --- /dev/null +++ b/.idea/Quartus_blink.iml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/inspectionProfiles/profiles_settings.xml b/.idea/inspectionProfiles/profiles_settings.xml new file mode 100644 index 0000000..105ce2d --- /dev/null +++ b/.idea/inspectionProfiles/profiles_settings.xml @@ -0,0 +1,6 @@ + + + + \ No newline at end of file diff --git a/.idea/modules.xml b/.idea/modules.xml new file mode 100644 index 0000000..3bda435 --- /dev/null +++ b/.idea/modules.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/vcs.xml b/.idea/vcs.xml new file mode 100644 index 0000000..35eb1dd --- /dev/null +++ b/.idea/vcs.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/blink.qar b/blink.qar new file mode 100644 index 0000000..ad7211b Binary files /dev/null and b/blink.qar differ diff --git a/blink.qarlog b/blink.qarlog new file mode 100644 index 0000000..7df8268 --- /dev/null +++ b/blink.qarlog @@ -0,0 +1,23 @@ +Quartus II Archive log -- C:/altera/13.1/workflow/blink.qarlog + +Archive: C:/altera/13.1/workflow/blink.qar +Date: Tue Apr 28 17:50:03 2026 +Quartus II 64-Bit 13.1.0 Build 162 10/23/2013 SJ Web Edition + + =========== Files Selected: =========== +C:/altera/13.1/workflow/blink.qpf +C:/altera/13.1/workflow/blink.qsf +C:/altera/13.1/workflow/blink.sdc +C:/altera/13.1/workflow/blink.v +C:/altera/13.1/workflow/db/blink.cmp.hdb +C:/altera/13.1/workflow/db/blink.db_info +C:/altera/13.1/workflow/incremental_db/compiled_partitions/blink.db_info +C:/altera/13.1/workflow/output_file.cof +C:/altera/13.1/workflow/output_files/Chain1.cdf +C:/altera/13.1/workflow/signalprobe_qsf.tcl +C:/altera/13.1/workflow/tb_blink.v +c:/altera/13.1/quartus/bin64/assignment_defaults.qdf + ======= Total: 12 files to archive ======= + + ================ Status: =============== +All files archived successfully. diff --git a/blink.qpf b/blink.qpf new file mode 100644 index 0000000..869a07d --- /dev/null +++ b/blink.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:43:14 March 05, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "23:43:14 March 05, 2026" + +# Revisions + +PROJECT_REVISION = "blink" diff --git a/blink.qsf b/blink.qsf new file mode 100644 index 0000000..ca0e31f --- /dev/null +++ b/blink.qsf @@ -0,0 +1,64 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:43:14 March 05, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# blink_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE6E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY blink +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:43:14 MARCH 05, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name VERILOG_FILE blink.v +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_23 -to clk +set_location_assignment PIN_87 -to led +set_global_assignment -name SDC_FILE blink.sdc +set_global_assignment -name CDF_FILE output_files/Chain1.cdf +set_global_assignment -name VERILOG_FILE tb_blink.v +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/blink.sdc b/blink.sdc new file mode 100644 index 0000000..29cb6da --- /dev/null +++ b/blink.sdc @@ -0,0 +1,3 @@ +create_clock -period 20 -name clk [get_ports clk] + + diff --git a/blink.v b/blink.v new file mode 100644 index 0000000..3818e5f --- /dev/null +++ b/blink.v @@ -0,0 +1,21 @@ +module blink( + input clk, + output reg led +); + +localparam MAX_COUNT = 50_000_000 - 1; // для 50 MHz → ~1 секунда + +reg [26:0] cnt;// 2^26 = 67_108_864 + +always @(posedge clk) +begin + if(cnt >= MAX_COUNT) + begin + cnt <= 0; + led <= ~led; // переключение LED + end + else + cnt <= cnt + 1; +end + +endmodule diff --git a/blink_description.txt b/blink_description.txt new file mode 100644 index 0000000..e69de29 diff --git a/output_file.cof b/output_file.cof new file mode 100644 index 0000000..7953721 --- /dev/null +++ b/output_file.cof @@ -0,0 +1,22 @@ + + + EPCS64 + EP4CE6 + output_file.jic + 1 + 1 + 7 + + Page_0 + 1 + + C:/altera/13.1/workflow/output_files/blink.sof + + + 5 + 0 + 0 + + 1 + + \ No newline at end of file diff --git a/output_file.map b/output_file.map new file mode 100644 index 0000000..ed66271 --- /dev/null +++ b/output_file.map @@ -0,0 +1,11 @@ +BLOCK START ADDRESS END ADDRESS + +Page_0 0x00000000 0x00059D8A + + + +Notes: + +- Data checksum for this conversion is 0x1A5EA7E1 + +- All the addresses in this file are byte addresses \ No newline at end of file diff --git a/signalprobe_qsf.tcl b/signalprobe_qsf.tcl new file mode 100644 index 0000000..3b3577b --- /dev/null +++ b/signalprobe_qsf.tcl @@ -0,0 +1,29 @@ +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# File: signalprobe_qsf.tcl +# Generated on: Mon Mar 09 21:03:20 2026 + +# Note: This file contains a Tcl script generated from the SignalProbe Gui. +# You can use this script to restore SignalProbes after deleting the DB +# folder; at the command line use "quartus_cdb -t signalprobe_qsf.tcl". + +package require ::quartus::chip_planner +package require ::quartus::project +project_open blink -revision blink +read_netlist +set had_failure 0 + diff --git a/tb_blink.v b/tb_blink.v new file mode 100644 index 0000000..95cb0bf --- /dev/null +++ b/tb_blink.v @@ -0,0 +1,44 @@ +`timescale 1ns/1ps + +module tb_blink; + +reg clk; +wire led; + +blink DUT( + .clk(clk), + .led(led) +); + +// Clock generator (50 MHz) +always #10 clk = ~clk; + +// Self checking logic +integer error_count = 0; +reg led_prev; + +initial begin + clk = 0; + led_prev = 0; + + #100000; // simulate time + + if(error_count == 0) + $display("SELF CHECK PASSED"); + else + $display("SELF CHECK FAILED, errors = %d", error_count); + + $stop; +end + +// Check LED toggle behavior +always @(posedge clk) +begin + #1; + if(led == led_prev) + error_count = error_count + 1; + + led_prev = led; +end + +endmodule \ No newline at end of file