pavel/Logic2_to_FPGA
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This commit is contained in:
irobo 2026-06-01 16:41:22 +03:00
parent 5ec983c2bd
commit 37f31f7dcb
3 changed files with 105 additions and 53 deletions
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52
digital_cut_50.csv Normal file
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@ -0,0 +1,52 @@
Time [s],Channel 7
0.000000000,0
0.000085333,1
0.000085625,0
0.000085833,1
0.000086000,0
0.000086417,1
0.000086583,0
0.000087000,1
0.000087167,0
0.000087625,1
0.000088042,0
0.000088208,1
0.000088625,0
0.000088833,1
0.000089000,0
0.000089417,1
0.000089583,0
0.000090000,1
0.000090417,0
0.000090625,1
0.000091042,0
0.000091208,1
0.000091625,0
0.000091833,1
0.000092000,0
0.000092417,1
0.000092833,0
0.000093000,1
0.000093167,0
0.000093625,1
0.000093792,0
0.000094208,1
0.000094375,0
0.000094833,1
0.000095208,0
0.000095417,1
0.000095833,0
0.000096000,1
0.000096167,0
0.000096625,1
0.000096792,0
0.000097208,1
0.000097625,0
0.000097833,1
0.000098208,0
0.000098417,1
0.000098833,0
0.000099000,1
0.000099167,0
0.000099583,1
0.000100167,0
1 Time [s] Channel 7
2 0.000000000 0
3 0.000085333 1
4 0.000085625 0
5 0.000085833 1
6 0.000086000 0
7 0.000086417 1
8 0.000086583 0
9 0.000087000 1
10 0.000087167 0
11 0.000087625 1
12 0.000088042 0
13 0.000088208 1
14 0.000088625 0
15 0.000088833 1
16 0.000089000 0
17 0.000089417 1
18 0.000089583 0
19 0.000090000 1
20 0.000090417 0
21 0.000090625 1
22 0.000091042 0
23 0.000091208 1
24 0.000091625 0
25 0.000091833 1
26 0.000092000 0
27 0.000092417 1
28 0.000092833 0
29 0.000093000 1
30 0.000093167 0
31 0.000093625 1
32 0.000093792 0
33 0.000094208 1
34 0.000094375 0
35 0.000094833 1
36 0.000095208 0
37 0.000095417 1
38 0.000095833 0
39 0.000096000 1
40 0.000096167 0
41 0.000096625 1
42 0.000096792 0
43 0.000097208 1
44 0.000097625 0
45 0.000097833 1
46 0.000098208 0
47 0.000098417 1
48 0.000098833 0
49 0.000099000 1
50 0.000099167 0
51 0.000099583 1
52 0.000100167 0

102
pattern_rom.v
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@ -1,4 +1,4 @@
// Автогенерация из CSV: Logic2_D7.csv // Автогенерация из CSV: digital_cut_50.csv
// F_CLK_HZ = 48000000 // F_CLK_HZ = 48000000
// Количество сегментов (DEPTH) = 50 // Количество сегментов (DEPTH) = 50
@ -13,56 +13,56 @@ module pattern_rom #(
// Простейший ROM на case по адресу // Простейший ROM на case по адресу
always @* begin always @* begin
case (addr) case (addr)
0: data = {1'b0, 32'd1}; 0: data = {1'b0, 32'd4096};
1: data = {1'b1, 32'd1}; 1: data = {1'b1, 32'd14};
2: data = {1'b0, 32'd1}; 2: data = {1'b0, 32'd10};
3: data = {1'b1, 32'd1}; 3: data = {1'b1, 32'd8};
4: data = {1'b0, 32'd1}; 4: data = {1'b0, 32'd20};
5: data = {1'b1, 32'd1}; 5: data = {1'b1, 32'd8};
6: data = {1'b0, 32'd1}; 6: data = {1'b0, 32'd20};
7: data = {1'b1, 32'd1}; 7: data = {1'b1, 32'd8};
8: data = {1'b0, 32'd1}; 8: data = {1'b0, 32'd22};
9: data = {1'b1, 32'd1}; 9: data = {1'b1, 32'd20};
10: data = {1'b0, 32'd1}; 10: data = {1'b0, 32'd8};
11: data = {1'b1, 32'd1}; 11: data = {1'b1, 32'd20};
12: data = {1'b0, 32'd1}; 12: data = {1'b0, 32'd10};
13: data = {1'b1, 32'd1}; 13: data = {1'b1, 32'd8};
14: data = {1'b0, 32'd1}; 14: data = {1'b0, 32'd20};
15: data = {1'b1, 32'd1}; 15: data = {1'b1, 32'd8};
16: data = {1'b0, 32'd1}; 16: data = {1'b0, 32'd20};
17: data = {1'b1, 32'd1}; 17: data = {1'b1, 32'd20};
18: data = {1'b0, 32'd1}; 18: data = {1'b0, 32'd10};
19: data = {1'b1, 32'd1}; 19: data = {1'b1, 32'd20};
20: data = {1'b0, 32'd1}; 20: data = {1'b0, 32'd8};
21: data = {1'b1, 32'd1}; 21: data = {1'b1, 32'd20};
22: data = {1'b0, 32'd1}; 22: data = {1'b0, 32'd10};
23: data = {1'b1, 32'd1}; 23: data = {1'b1, 32'd8};
24: data = {1'b0, 32'd1}; 24: data = {1'b0, 32'd20};
25: data = {1'b1, 32'd1}; 25: data = {1'b1, 32'd20};
26: data = {1'b0, 32'd1}; 26: data = {1'b0, 32'd8};
27: data = {1'b1, 32'd1}; 27: data = {1'b1, 32'd8};
28: data = {1'b0, 32'd1}; 28: data = {1'b0, 32'd22};
29: data = {1'b1, 32'd1}; 29: data = {1'b1, 32'd8};
30: data = {1'b0, 32'd1}; 30: data = {1'b0, 32'd20};
31: data = {1'b1, 32'd1}; 31: data = {1'b1, 32'd8};
32: data = {1'b0, 32'd1}; 32: data = {1'b0, 32'd22};
33: data = {1'b1, 32'd1}; 33: data = {1'b1, 32'd18};
34: data = {1'b0, 32'd1}; 34: data = {1'b0, 32'd10};
35: data = {1'b1, 32'd1}; 35: data = {1'b1, 32'd20};
36: data = {1'b0, 32'd1}; 36: data = {1'b0, 32'd8};
37: data = {1'b1, 32'd1}; 37: data = {1'b1, 32'd8};
38: data = {1'b0, 32'd1}; 38: data = {1'b0, 32'd22};
39: data = {1'b1, 32'd1}; 39: data = {1'b1, 32'd8};
40: data = {1'b0, 32'd1}; 40: data = {1'b0, 32'd20};
41: data = {1'b1, 32'd1}; 41: data = {1'b1, 32'd20};
42: data = {1'b0, 32'd1}; 42: data = {1'b0, 32'd10};
43: data = {1'b1, 32'd1}; 43: data = {1'b1, 32'd18};
44: data = {1'b0, 32'd1}; 44: data = {1'b0, 32'd10};
45: data = {1'b1, 32'd1}; 45: data = {1'b1, 32'd20};
46: data = {1'b0, 32'd1}; 46: data = {1'b0, 32'd8};
47: data = {1'b1, 32'd1}; 47: data = {1'b1, 32'd8};
48: data = {1'b0, 32'd1}; 48: data = {1'b0, 32'd20};
49: data = {1'b1, 32'd1}; 49: data = {1'b1, 32'd28};
default: data = {1'b0, {TICKS_WIDTH{1'b0}}}; default: data = {1'b0, {TICKS_WIDTH{1'b0}}};
endcase endcase
end end

4
to_FPGA.py
View File

@ -6,7 +6,7 @@ from pathlib import Path
# ========================== # ==========================
# Входной файл из Logic 2 (CSV только с Time [s] и D7) # Входной файл из Logic 2 (CSV только с Time [s] и D7)
CSV_FILE = "Logic2_D7.csv" CSV_FILE = "digital_cut_50.csv"
# Выходной Verilog-файл # Выходной Verilog-файл
VERILOG_FILE = "pattern_rom.v" VERILOG_FILE = "pattern_rom.v"
@ -16,7 +16,7 @@ F_CLK_HZ = 48_000_000 # пример: 48 МГц
# Имена колонок в CSV (посмотри заголовок в своём файле и подгони при необходимости) # Имена колонок в CSV (посмотри заголовок в своём файле и подгони при необходимости)
TIME_COL = "Time [s]" # колонка с временем TIME_COL = "Time [s]" # колонка с временем
LEVEL_COL = "D7" # колонка с уровнем сигнала LEVEL_COL = "Channel 7" # колонка с уровнем сигнала
# Сколько бит отвести под счётчик тиков в Verilog # Сколько бит отвести под счётчик тиков в Verilog
TICKS_WIDTH = 32 TICKS_WIDTH = 32