462 lines
11 KiB
Verilog
462 lines
11 KiB
Verilog
module PCON_DATA_IO (clockin, FO_INPUT, FO_OUTP, DATA_TO_SEND, DATA_RECIEVED, DATA_CLOCK, IO_ERR);
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input FO_INPUT;
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input clockin;
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input [155:0] DATA_TO_SEND;
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output FO_OUTP;
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output [155:0] DATA_RECIEVED;
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output DATA_CLOCK;
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output [2:0] IO_ERR;
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reg [7:0] FO_INPUT_CRITICAL_DATA;
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reg [95:0] FO_INPUT_REGULAR_DATA;
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reg [15:0] TRANSMITT_DATA_VALUE;
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reg [7:0] TX_SM_COUNTER;
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reg [4:0] TX_SM_STATE;
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reg [4:0] TX_BIT_COUNTER;
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reg [4:0] TX_VAL_NUM_COUNTER;
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reg [4:0] TX_SLOW_VAL_NUM_COUNTER;
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reg [155:0] DATA_OUTPUT_VALUE;
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reg FO_OUTPUT;
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reg DATA_READY;
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reg ERROR_FLAG;
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reg CRITICAL_ERROR_FLAG;
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reg NOTRANSMITTION_FAULT_FLAG;
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reg [2:0] ERROR_OUTPUT;
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reg [15:0] NOCHANGE_COUNTER;
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reg ERROR_FLAG_COUNTER;
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reg ERROR_FLAG_COUNTER_PREV;
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reg CRITICAL_ERROR_FLAG_COUNTER;
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reg FO_INPUT_REG;
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reg FO_INPUT_PREV;
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reg [63:0] RX_DATA_READ_VALUE;
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reg [11:0] RX_DATA_VALUE;
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reg [11:0] RX_DATA_CHECK_VALUE;
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reg [7:0] RX_CRITICAL_DATA_VALUE;
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reg [7:0] RX_CRITICAL_DATA_CHECK_VALUE;
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reg [3:0] RX_DATA_NUM;
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reg [3:0] RX_DATA_NUM_CHECK;
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reg [3:0] RX_SLOW_VAL_NUM_COUNTER;
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reg [15:0] RX_SM_STATE;
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reg [15:0] RX_SM_COUNTER;
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reg [5:0] RX_BIT_COUNTER;
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reg [5:0] RX_BIT_COUNTER_OLD;
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reg [15:0] RX_POSVAL_COUNTER;
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reg [15:0] RX_NEGVAL_COUNTER;
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reg [15:0] RX_CHECKVAL_COUNTER;
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//assign FO_OUTP = ~FO_OUTPUT; //NORMAL
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assign FO_OUTP = FO_OUTPUT; //TEMP INVERSE!!!!!!!
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assign DATA_RECIEVED = DATA_OUTPUT_VALUE;
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assign DATA_CLOCK = DATA_READY;
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assign IO_ERR = ERROR_OUTPUT;
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initial
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begin
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TX_SM_COUNTER = 0;
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TX_SM_STATE = 0;
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TX_BIT_COUNTER=0;
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TX_VAL_NUM_COUNTER=0;
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end
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always@(posedge clockin)
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begin
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//TRANSMITT --------------------------------------------------
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if (TX_SM_STATE==0) //Generate start signal
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begin
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TX_SM_COUNTER <= TX_SM_COUNTER + 1;
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if (TX_SM_COUNTER>75)
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begin
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TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[7:0];
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FO_OUTPUT <= 0;
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TX_SM_STATE <= 1;
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TX_SM_COUNTER <= 0;
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TX_BIT_COUNTER <= 0;
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end
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else
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begin
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FO_OUTPUT<=0;
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end
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end
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else if (TX_SM_STATE==1) //Transmitt critical data
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begin
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TX_SM_COUNTER <= TX_SM_COUNTER + 1;
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if (TX_SM_COUNTER==28)
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begin
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TX_SM_COUNTER<=0;
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TX_BIT_COUNTER <= TX_BIT_COUNTER+1;
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if (TX_BIT_COUNTER==7)
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begin
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FO_OUTPUT <= 0;
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TX_SM_STATE <= 2;
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TX_SM_COUNTER <= 0;
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TX_BIT_COUNTER <= 0;
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end
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end
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if (TX_SM_COUNTER==0)
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begin
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FO_OUTPUT <= 1;
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end
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if (TRANSMITT_DATA_VALUE[TX_BIT_COUNTER]==0)
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begin
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if (TX_SM_COUNTER==8)
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begin
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FO_OUTPUT<=0;
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end
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end
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else
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begin
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if (TX_SM_COUNTER==20)
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begin
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FO_OUTPUT<=0;
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end
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end
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end
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else if (TX_SM_STATE==2) //Repeat critical data transmittion
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begin
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TX_SM_COUNTER <= TX_SM_COUNTER + 1;
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if (TX_SM_COUNTER==28)
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begin
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TX_SM_COUNTER<=0;
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TX_BIT_COUNTER <= TX_BIT_COUNTER+1;
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if (TX_BIT_COUNTER==7)
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begin
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if (TX_VAL_NUM_COUNTER==0)
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begin TRANSMITT_DATA_VALUE[11:0] <= DATA_TO_SEND[19:8]; end
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else if (TX_VAL_NUM_COUNTER==1)
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begin TRANSMITT_DATA_VALUE[11:0] <= DATA_TO_SEND[31:20]; end
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else if (TX_VAL_NUM_COUNTER==2)
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begin TRANSMITT_DATA_VALUE[11:0] <= DATA_TO_SEND[43:32]; end
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else if (TX_VAL_NUM_COUNTER==3)
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begin TRANSMITT_DATA_VALUE[11:0] <= DATA_TO_SEND[55:44]; end
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else if (TX_VAL_NUM_COUNTER==4)
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begin TRANSMITT_DATA_VALUE[11:0] <= DATA_TO_SEND[67:56]; end
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else if (TX_VAL_NUM_COUNTER==5)
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begin TRANSMITT_DATA_VALUE[11:0] <= DATA_TO_SEND[79:68]; end
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else if (TX_VAL_NUM_COUNTER==6)
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begin TRANSMITT_DATA_VALUE[11:0] <= DATA_TO_SEND[91:80]; end
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else if (TX_VAL_NUM_COUNTER==7)
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begin
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TRANSMITT_DATA_VALUE[11:8] = TX_SLOW_VAL_NUM_COUNTER;
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if (TX_SLOW_VAL_NUM_COUNTER==0) begin TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[99:92]; end
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if (TX_SLOW_VAL_NUM_COUNTER==1) begin TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[107:100]; end
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if (TX_SLOW_VAL_NUM_COUNTER==2) begin TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[115:108]; end
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if (TX_SLOW_VAL_NUM_COUNTER==3) begin TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[123:116]; end
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if (TX_SLOW_VAL_NUM_COUNTER==4) begin TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[131:124]; end
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if (TX_SLOW_VAL_NUM_COUNTER==5) begin TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[139:132]; end
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if (TX_SLOW_VAL_NUM_COUNTER==6) begin TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[147:140]; end
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if (TX_SLOW_VAL_NUM_COUNTER==7) begin TRANSMITT_DATA_VALUE[7:0] <= DATA_TO_SEND[155:148]; end
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end
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TRANSMITT_DATA_VALUE[15:12] <= TX_VAL_NUM_COUNTER;
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FO_OUTPUT <= 1;
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TX_SM_STATE <= 3;
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TX_SM_COUNTER <= 0;
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TX_BIT_COUNTER <= 0;
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end
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end
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if (TX_SM_COUNTER==0)
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begin
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FO_OUTPUT <= 1;
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end
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if (TRANSMITT_DATA_VALUE[TX_BIT_COUNTER]==0)
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begin
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if (TX_SM_COUNTER==8)
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begin
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FO_OUTPUT<=0;
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end
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end
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else
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begin
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if (TX_SM_COUNTER==20)
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begin
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FO_OUTPUT<=0;
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end
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end
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end
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else if (TX_SM_STATE==3) //Transmitt regular data
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begin
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TX_SM_COUNTER <= TX_SM_COUNTER + 1;
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if (TX_SM_COUNTER==28)
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begin
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TX_SM_COUNTER<=0;
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TX_BIT_COUNTER <= TX_BIT_COUNTER+1;
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if (TX_BIT_COUNTER==15)
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begin
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FO_OUTPUT <= 1;
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TX_SM_STATE <= 4;
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TX_SM_COUNTER <= 0;
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TX_BIT_COUNTER <= 0;
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end
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end
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if (TX_SM_COUNTER==0)
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begin
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FO_OUTPUT <= 1;
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end
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if (TRANSMITT_DATA_VALUE[TX_BIT_COUNTER]==0)
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begin
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if (TX_SM_COUNTER==8)
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begin
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FO_OUTPUT<=0;
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end
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end
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else
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begin
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if (TX_SM_COUNTER==20)
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begin
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FO_OUTPUT<=0;
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end
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end
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end
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else if (TX_SM_STATE==4) //Repeat regular data transmittion
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begin
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TX_SM_COUNTER <= TX_SM_COUNTER + 1;
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if (TX_SM_COUNTER==28)
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begin
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TX_SM_COUNTER<=0;
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TX_BIT_COUNTER <= TX_BIT_COUNTER+1;
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if (TX_BIT_COUNTER==15)
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begin
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FO_OUTPUT <= 1;
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TX_SM_STATE <= 5;
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TX_SM_COUNTER <= 0;
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TX_BIT_COUNTER <= 0;
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end
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end
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if (TX_SM_COUNTER==0)
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begin
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FO_OUTPUT <= 1;
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end
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if (TRANSMITT_DATA_VALUE[TX_BIT_COUNTER]==0)
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begin
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if (TX_SM_COUNTER==8)
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begin
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FO_OUTPUT<=0;
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end
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end
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else
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begin
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if (TX_SM_COUNTER==20)
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begin
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FO_OUTPUT<=0;
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end
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end
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end
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else if (TX_SM_STATE==5) //End pulse generation
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begin
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TX_SM_COUNTER <= TX_SM_COUNTER + 1;
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FO_OUTPUT<=1;
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if (TX_SM_COUNTER==28)
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begin
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if (TX_VAL_NUM_COUNTER==7)
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begin
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if (TX_SLOW_VAL_NUM_COUNTER<7) begin TX_SLOW_VAL_NUM_COUNTER = TX_SLOW_VAL_NUM_COUNTER + 1; end
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else begin TX_SLOW_VAL_NUM_COUNTER=0; end
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TX_VAL_NUM_COUNTER = 0;
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end
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else
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begin
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TX_VAL_NUM_COUNTER = TX_VAL_NUM_COUNTER + 1;
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end
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FO_OUTPUT <= 0;
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TX_SM_STATE <= 0;
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TX_SM_COUNTER <= 0;
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TX_BIT_COUNTER <= 0;
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end
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end
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//TRANSMITT END-----------------------------------------------
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//RECIEVE ----------------------------------------------------
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FO_INPUT_REG = FO_INPUT;
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RX_SM_COUNTER = RX_SM_COUNTER + 1;
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ERROR_OUTPUT[0] = NOTRANSMITTION_FAULT_FLAG;
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ERROR_OUTPUT[1] = CRITICAL_ERROR_FLAG;
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ERROR_OUTPUT[2] = ERROR_FLAG;
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if (FO_INPUT_PREV!=FO_INPUT_REG)
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begin
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NOCHANGE_COUNTER = 0;
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NOTRANSMITTION_FAULT_FLAG = 0;
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if (FO_INPUT_PREV==0)
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begin
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if (RX_SM_COUNTER<3)
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begin
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if (RX_CHECKVAL_COUNTER<14)
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begin
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RX_DATA_READ_VALUE[RX_BIT_COUNTER] = 1;
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end
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else
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begin
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RX_DATA_READ_VALUE[RX_BIT_COUNTER] = 0;
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end
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end
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if (RX_SM_COUNTER>3)
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begin
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RX_POSVAL_COUNTER = 0;
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RX_NEGVAL_COUNTER = 0;
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RX_BIT_COUNTER_OLD = RX_BIT_COUNTER;
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end
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if (RX_SM_COUNTER>4)
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begin
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FO_INPUT_PREV = FO_INPUT_REG;
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end
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end
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else
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begin
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RX_CRITICAL_DATA_VALUE = RX_DATA_READ_VALUE[8:1];
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RX_CRITICAL_DATA_CHECK_VALUE = RX_DATA_READ_VALUE[16:9];
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RX_DATA_VALUE = RX_DATA_READ_VALUE[28:17];
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RX_DATA_NUM = RX_DATA_READ_VALUE[32:29];
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RX_DATA_CHECK_VALUE = RX_DATA_READ_VALUE[44:33];
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RX_DATA_NUM_CHECK = RX_DATA_READ_VALUE[48:45];
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RX_BIT_COUNTER = RX_BIT_COUNTER_OLD + 1;
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RX_SLOW_VAL_NUM_COUNTER = RX_DATA_READ_VALUE[28:25];
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if (RX_SM_COUNTER>4)
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begin
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FO_INPUT_PREV = FO_INPUT_REG;
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end
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end
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end
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else
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begin
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RX_SM_COUNTER = 0;
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if (NOCHANGE_COUNTER>250)
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begin
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NOTRANSMITTION_FAULT_FLAG = 1;
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end
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else
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begin
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NOCHANGE_COUNTER = NOCHANGE_COUNTER + 1;
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end
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end
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if (FO_INPUT_REG==1)
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begin
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RX_POSVAL_COUNTER = RX_POSVAL_COUNTER + 1;
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RX_NEGVAL_COUNTER = RX_NEGVAL_COUNTER;
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RX_CHECKVAL_COUNTER = RX_CHECKVAL_COUNTER;
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end
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else
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begin
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RX_NEGVAL_COUNTER = RX_NEGVAL_COUNTER + 1;
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RX_POSVAL_COUNTER = RX_POSVAL_COUNTER;
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RX_CHECKVAL_COUNTER = RX_NEGVAL_COUNTER;
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end
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if (RX_NEGVAL_COUNTER>50 && RX_NEGVAL_COUNTER<55)
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begin
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RX_BIT_COUNTER = 0;
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if (RX_CRITICAL_DATA_VALUE==RX_CRITICAL_DATA_CHECK_VALUE)
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begin
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DATA_OUTPUT_VALUE[7:0] = RX_CRITICAL_DATA_VALUE;
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CRITICAL_ERROR_FLAG = 0;
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CRITICAL_ERROR_FLAG_COUNTER=0;
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end
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else
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begin
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if (CRITICAL_ERROR_FLAG_COUNTER==1)
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begin
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CRITICAL_ERROR_FLAG = 1;
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DATA_OUTPUT_VALUE[7:0] = 0;
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end
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else
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begin
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CRITICAL_ERROR_FLAG_COUNTER = 1;
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DATA_OUTPUT_VALUE[7:0] = DATA_OUTPUT_VALUE[7:0];
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end
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end
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if ((RX_DATA_VALUE==RX_DATA_CHECK_VALUE) && (RX_DATA_NUM==RX_DATA_NUM_CHECK))
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begin
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if (RX_DATA_NUM==0)
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begin
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DATA_OUTPUT_VALUE[19:8] = RX_DATA_VALUE;
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ERROR_FLAG_COUNTER = 0;
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end
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else if (RX_DATA_NUM==1)
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begin DATA_OUTPUT_VALUE[31:20] = RX_DATA_VALUE; end
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else if (RX_DATA_NUM==2)
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begin DATA_OUTPUT_VALUE[43:32] = RX_DATA_VALUE; end
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else if (RX_DATA_NUM==3)
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begin DATA_OUTPUT_VALUE[55:44] = RX_DATA_VALUE; end
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else if (RX_DATA_NUM==4)
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begin DATA_OUTPUT_VALUE[67:56] = RX_DATA_VALUE; end
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else if (RX_DATA_NUM==5)
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begin DATA_OUTPUT_VALUE[79:68] = RX_DATA_VALUE; end
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else if (RX_DATA_NUM==6)
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begin DATA_OUTPUT_VALUE[91:80] = RX_DATA_VALUE; end
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else if (RX_DATA_NUM==7)
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begin
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if (RX_SLOW_VAL_NUM_COUNTER==0) begin DATA_OUTPUT_VALUE[99:92] = RX_DATA_VALUE[7:0]; end
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if (RX_SLOW_VAL_NUM_COUNTER==1) begin DATA_OUTPUT_VALUE[107:100] = RX_DATA_VALUE[7:0]; end
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if (RX_SLOW_VAL_NUM_COUNTER==2) begin DATA_OUTPUT_VALUE[115:108] = RX_DATA_VALUE[7:0]; end
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if (RX_SLOW_VAL_NUM_COUNTER==3) begin DATA_OUTPUT_VALUE[123:116] = RX_DATA_VALUE[7:0]; end
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if (RX_SLOW_VAL_NUM_COUNTER==4) begin DATA_OUTPUT_VALUE[131:124] = RX_DATA_VALUE[7:0]; end
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if (RX_SLOW_VAL_NUM_COUNTER==5) begin DATA_OUTPUT_VALUE[139:132] = RX_DATA_VALUE[7:0]; end
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if (RX_SLOW_VAL_NUM_COUNTER==6) begin DATA_OUTPUT_VALUE[147:140] = RX_DATA_VALUE[7:0]; end
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if (RX_SLOW_VAL_NUM_COUNTER==7) begin DATA_OUTPUT_VALUE[155:148] = RX_DATA_VALUE[7:0]; end
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if (ERROR_FLAG_COUNTER==0 && ERROR_FLAG_COUNTER_PREV==0)
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begin
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ERROR_FLAG = 0;
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end
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else
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begin
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ERROR_FLAG_COUNTER_PREV = ERROR_FLAG_COUNTER;
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end
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end
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end
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else
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begin
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if (ERROR_FLAG_COUNTER_PREV==1)
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begin
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ERROR_FLAG = 1;
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end
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else
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begin
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ERROR_FLAG_COUNTER = 1;
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end
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end
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end
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if (RX_NEGVAL_COUNTER>55)
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begin
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RX_CRITICAL_DATA_VALUE = 0;
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RX_CRITICAL_DATA_CHECK_VALUE = 0;
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RX_DATA_VALUE = 0;
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RX_DATA_NUM = 0;
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RX_DATA_CHECK_VALUE = 0;
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RX_DATA_NUM_CHECK = 0;
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RX_DATA_READ_VALUE = 0;
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end
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//RECIEVE END-------------------------------------------------
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end
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endmodule
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